CODEWITHSUNDEEP
gem5
Will Hahn
Will Hahn

Reputation: 21

gem5: how can i monitor when branch misprediction happened during simulating O3CPU?

I'm currently planning to build a IPC performance counter for Out-Of-Order(O3) CPU using gem5. I've read a paper about building an accurate performance counter for O3 CPU and the idea is using top-down interval analysis.(The paper is A Performance Counter Architecture for Computing Accurate CPI Components) So I'm planning to apply this idea and in order to do this, I have to capture the moment when branch misprediction, I-Cache miss, D-cache miss, ... etc happen and increase counters for each events. I've looked up gem5/src/cpu/o3/decode.cc and there are lines about mispredictions like below.

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I'm trying to write codes like below (I think I should create a new object for IPC counter)

if(decodeInfo[tid].branchMispredict == true) counter++;

but I'm struggling to find where to start.

thanks for reading.

Upvotes: 2

Views: 611

Answers (1)

Adrián Herrera Arcila
Adrián Herrera Arcila

Reputation: 78

gem5 provides a statistics framework to capture hardware events. The O3 CPU model already implements a large number of statistics, including for branch mispredictions (at decode and execute). I suggest you to have a look at them and assess whether they're sufficient for your needs.

Statistics are reported at the end of the simulation in m5out/stats.txt.

PS: statistics are completely accurate and costless, they do not have limitations such as capturing every N cycles or overhead of communicating values to software, for example via interrupts. If you need to model those, you may want to use a performance counter model, such as the Arm PMU model.

Upvotes: 0

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