CODEWITHSUNDEEP
system-verilog
mmillar10
mmillar10

Reputation: 23

Is there a method to execute a block of code after a user calls $finish?

We want to be able to provide a predefined list of things to be done at the end of every SystemVerilog test. Since multiple people are working on this project, it'd be nice if they did not have to think about the things we are doing in the background, but simply call $finish at the end of a test as usual. I know we could create our own custom $finish macro, but we would prefer to not have to change preexisting tests.

Is there any way in SystemVerilog to have a block of code run after a $finish call? Using something like UVM is not an option. I've looked around, but I can't seem to find something that does this behavior.

Upvotes: 2

Views: 1045

Answers (2)

dave_59
dave_59

Reputation: 42788

If the list of things does not consume time, a final block is the antithesis of an initial block, except it cannot consume any time. Otherwise, it would not be the "final" thing.

If you need steps that consume time, there is no way of doing this without modifying the existing tests. The simplest approach is declaring a global event like test_done in a package p, and then replacing $finish; with ->p::test_done;. But sometimes you need to shut down other free-running process. Doing that requires much more coordination, which is exactly what UVM accomplishes with its phases and objections mechanism.

Upvotes: 2

toolic
toolic

Reputation: 62236

The final keyword can help you out here. Refer to IEEE Std 1800-2017, section 9.2.3 Final procedures:

A final procedure executes when simulation ends due to an explicit or implicit call to $finish .

One limitation is that it executes in zero time, which means you can not have any delays, etc. Read the full description for all the details.

Example:

final begin
    $display("something");
    do_something();
end

Upvotes: 3

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