Reputation: 8610
On a Raspberry Pi 3b, which is ARM Cortex-A5 processor, ARMv7 architecture, I am reading the cycle counter registers from the PMU (Performance Monitor Unit):
uint32_t cycle_counter_read (void)
{
uint32_t cc = 0;
__asm__ volatile ("mrc p15, 0, %0, c9, c13, 0":"=r" (cc));
return cc;
}
I'd like to understand on which ARM processors will this code run successfully, other than the one in Raspberry Pi 3B. Which ARM info is important for this:
Upvotes: 0
Views: 726
Reputation: 67802
I'd like to understand on which ARM processors will this code run successfully, other than the one in Raspberry Pi 3B. Which ARM info is important for this
Well, mrc p15
is moving into a register from coprocessor 15.
So, the important info is just whether the processor has a PMU on coprocessor #15.
I think the feature is optional (although strongly recommended), so it's always possible you'll come across a custom ARM chip that doesn't have a PMU. Hopefully it's always on coprocessor #15 at least, when it is present.
Probably the best you can do is find a list of chips known to have one. You can use the ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0
on ARM v8, but I don't know of a reliable mechanism before that.
Searching for "arm pmu" found, for example this list in the Linux kernel documentation:
ARM cores often have a PMU for counting cpu and cache events like cache misses
and hits.
...
- compatible : should be one of
"apm,potenza-pmu"
"arm,armv8-pmuv3"
"arm,cortex-a73-pmu"
"arm,cortex-a72-pmu"
"arm,cortex-a57-pmu"
"arm,cortex-a53-pmu"
"arm,cortex-a35-pmu"
"arm,cortex-a17-pmu"
"arm,cortex-a15-pmu"
"arm,cortex-a12-pmu"
"arm,cortex-a9-pmu"
"arm,cortex-a8-pmu"
"arm,cortex-a7-pmu"
"arm,cortex-a5-pmu"
"arm,arm11mpcore-pmu"
"arm,arm1176-pmu"
"arm,arm1136-pmu"
"brcm,vulcan-pmu"
"cavium,thunder-pmu"
"qcom,scorpion-pmu"
"qcom,scorpion-mp-pmu"
"qcom,krait-pmu"
Upvotes: 2