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linux-kernelarminterruptarm64device-tree
linuxer
linuxer

Reputation: 21

Why would a Linux GPIO controller use a hierarchicy IRQ domain?

I am trying to understand the "IRQ domain hierarchy" in Linux kernel's ARM interrupts subsystem. In struct irq_domain_ops,there is a macro CONFIG_IRQ_DOMAIN_HIERARCHY.

On this ARM platform, intc is a GIC-400 (the root interrupt-controller) and gpio1 is both a gpio-controller and an interrupt-controller. My understanding is that gpio1 and intc are each their own IRQ domain, but I do not understand the "hierarchy" structure.

The DTS is as follows:

intc: interrupt-controller@00a01000 {//root interrupt controller
    compatible = "arm,cortex-a7-gic";
    #interrupt-cells = <3>;
    interrupt-controller;
    reg = <0x00a01000 0x1000>,
          <0x00a02000 0x100>;
};

gpio1: gpio@0209c000 {
    compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
    reg = <0x0209c000 0x4000>;
    interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
};

What is the purpose of having a "hierarchy" of IRQ domains?

My test enviroment is: linux 4.1.15

Upvotes: 2

Views: 419

Answers (1)

Woodrow Barlow
Woodrow Barlow

Reputation: 9097

It is common for a GPIO controller to also behave as an interrupt controller. This allows other drivers to request a mapping between a GPIO descriptor and its underlying hwirq value via gpiod_to_irq() or via device tree, like:

my_label: node@0 {
    [ ... ]
    /* we're getting the interrupt by GPIO pin number instead of from the GIC */
    interrupt-parent = <&gpio1>;
    interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
};

Most software already knows which GPIO it is interested in, but might not know which interrupt lane corresponds to that GPIO. This mapping enables software to resolve that information at runtime.

This GPIO-to-irq mapping is also required to use libgpio for userspace GPIO interrupts.

There are two common scenarios in which one might want the GPIO controller to also behave as an interrupt controller:

  • The GPIO controller is a "cascaded interrupt chip", meaning it really is an interrupt controller/mux at the hardware level. This is not the case in your scenario.
  • You want to register the GPIO controller as a "hierarchical interrupt chip", meaning each GPIO line is connected to an upstream interrupt controller, such as the GIC400 in your case. In this case it means the GPIO controller is acting as a "virtual" interrupt controller, with its own "virtual" irq_domain, all to provide a convenient mapping between GPIO number and hwirq value.

For more information, please refer to the documentation for the GPIO sub-system, section "GPIO drivers providing IRQs" and the documentation for Hierarchical IRQ Domains in the core API.

Upvotes: 0

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