CODEWITHSUNDEEP
system-verilogsystem-verilog-assertions
AmV
AmV

Reputation: 11

How to use an input value with repetition operator?

How I can use a design input with the repetition operator in a SV assertion? Basically, what I'm trying to implement is:

property ( ( disable iff((a) or (b) or (c) or (d))
          $rose(req) |-> req[*32]

I'm trying to replace the 32 with t_req, which is an input to the design module and can be changed by the user.

Is there any way to make the assertion dynamic so that the value 32 is not hardcoded?

Upvotes: 1

Views: 416

Answers (1)

Matthew
Matthew

Reputation: 14007

One way is to count how long req is high for and then to compare that with t_req. To do that, you need to embed some code inside your assertion. You can do that using this operator:

( <a sequence>, <some code>, <some more code>, ...)

When the sequence matches, the code is executed. You cannot write any code. There are only 3 things you can do:

  • assign to a local variable
  • increment/decrement a local variable
  • call a function or task

A local variable is one declared within the property. The function or task must not assign to any other variables.

So, here is a suggestion:

property req_check;
    int unsigned pulse_width;
    ($rose(req), pulse_width=0) |-> (req, pulse_width++) ##1 (!req && check(pulse_width) );
endproperty

assert property ( disable iff ((a) or (b) or (c) or (d)) req_check);

function bit check(int unsigned width);
    return (width == t_req);
endfunction

Upvotes: 0

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