CODEWITHSUNDEEP
constantssystem-veriloggenerate
wzab
wzab

Reputation: 830

How to create a named constant in the SystemVerilog generate block?

I need to transmit a set of values between the SystemVerilog and VHDL code. To do that, I have to flatten the SV structures into the bit vectors, transmit the bit vectors, and rebuild the structures at the VHDL side. Unfortunately, I have faced a serious problem at the SV side. My "flattener" has the following code:

   generate
    for(genvar i=0;i<nlinks;i++)
      for(genvar j=0;j<2;j++)
        begin
        const int base = 2 * i + j;
           assign vf[base] = lct_aligned[i][j].vf;
           assign hs[(8*base+7):8*base] = lct_aligned[i][j].hs;
           assign wg[(7*base+6):7*base] = lct_aligned[i][j].wg;
           assign ql[(4*base+3):4*base] = lct_aligned[i][j].ql;
           assign cp[(4*base+3):4*base] = lct_aligned[i][j].cp;
           assign lr[base] = lct_aligned[i][j].lr;
           assign bc0[base] = lct_aligned[i][j].bc0;
           assign bx0[base] = lct_aligned[i][j].bx0;
           assign ser[base] = lct_aligned[i][j].ser;
           assign cid[(4*base+3):4*base] = lct_aligned[i][j].cid;          
        end 
     endgenerate

Unfortunately, it gives "base is not a constant error" in each "assign" line. When I replace "base" with "(2*i+j)" the code compiles correctly, but is significantly less visible and mantainable.

   generate
    for(genvar i=0;i<nlinks;i++)
      for(genvar j=0;j<2;j++)
        begin
           //const int base = 2 * i + j;
           assign vf[(2*i+j)] = lct_aligned[i][j].vf;
           assign hs[(8*(2*i+j)+7):8*(2*i+j)] = lct_aligned[i][j].hs;
           assign wg[(7*(2*i+j)+6):7*(2*i+j)] = lct_aligned[i][j].wg;
           assign ql[(4*(2*i+j)+3):4*(2*i+j)] = lct_aligned[i][j].ql;
           assign cp[(4*(2*i+j)+3):4*(2*i+j)] = lct_aligned[i][j].cp;
           assign lr[(2*i+j)] = lct_aligned[i][j].lr;
           assign bc0[(2*i+j)] = lct_aligned[i][j].bc0;
           assign bx0[(2*i+j)] = lct_aligned[i][j].bx0;
           assign ser[(2*i+j)] = lct_aligned[i][j].ser;
           assign cid[(4*(2*i+j)+3):4*(2*i+j)] = lct_aligned[i][j].cid;        
        end 
     endgenerate

Is there any way to define constants for complex expressions in the SystemVerilog generate blocks?

Upvotes: 0

Views: 670

Answers (1)

dave_59
dave_59

Reputation: 42698

A const variable is not really a constant. It's a variable with a write once at run-time value. A parameter or localparam is a compile time constant. Simply replace const with parameter.

Upvotes: 1

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