CODEWITHSUNDEEP
yosysnextpnr
Hammdist
Hammdist

Reputation: 11

why are SB_LUT4 and SB_DFF not being packed by nextpnr?

I added the yosys tag, though this question is probably more about nextpnr (which has no tag on this site).

I'm using yosys with nextpnr-ice40 on the following file.

When I dump the design with --post-route /path/to/nextpnr/python/dump_design.py (I didn't bother with the GUI), it seems as though it's using separate logic units for the DFF as for LUT4, whereas I would expect it to fuse them into one logic unit using the logic unit's built-in DFF.

In my run they end up on Bels X12/Y12/lc4 and X12/Y12/lc2, and the logic unit that hosts the LUT4 has the DFF disabled.

Am I not doing it correctly? I tried swapping the order of the instantiations in the input file to no avail.

module top(input clk, output blinky);
   wire clk2;
   wire blinky2;
   wire blinky3;
   SB_IO #(
           .PIN_TYPE(6'b 1010_01),
           .PULLUP(1'b 0)
           ) clk_buf (
                      .PACKAGE_PIN(clk),
                      .OUTPUT_ENABLE(1'b0),
                      .D_OUT_0(1'b0),
                      .D_IN_0(clk2)
                      );
   SB_IO #(
           .PIN_TYPE(6'b 1010_01),
           .PULLUP(1'b 0)
           ) blinky_buf (
                      .PACKAGE_PIN(blinky),
                      .OUTPUT_ENABLE(1'b1),
                      .D_OUT_0(blinky2)
                      );
   SB_LUT4 #(
             .LUT_INIT(16'b0000_0000_0000_0000)
             ) lut(blinky2, blinky3, blinky3, blinky3, blinky3);
   SB_DFF dff(blinky3 /* O */, clk2, blinky2 /* D */);
endmodule

Upvotes: 0

Views: 159

Answers (1)

Hammdist
Hammdist

Reputation: 11

Ah, found the answer myself. It's the .D_OUT_0(blinky2) that is preventing the packing optimization, as it requires the value before the DFF. Changing that to .D_OUT_0(blinky3) exhibits packing.

Upvotes: 0

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