CODEWITHSUNDEEP
syntaxverilog
abunickabhi
abunickabhi

Reputation: 578

Multiple variables in Verilog case structure control expression

I am using case statement to write my Verilog logic. I wanted to know if we can AND multiple variables in the case's control expression.

reg a;
reg [5:0] b;
reg c;
case(a & b)
    1'b0 & 6'd0: c <= 1'b1;
    1'b1 & 6'd1: c <= 1'b0;
    default: c <= 1'b0;
endcase

Upvotes: 0

Views: 2522

Answers (1)

dave_59
dave_59

Reputation: 42673

What you want is a concatenation {} not and &

case({a,b})
    {1'b0 , 6'd0}: c <= 1'b1;
    {1'b1 , 6'd1}: c <= 1'b0;
    default: c <= 1'b0;
endcase

Upvotes: 2

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