Reputation: 11
I am making a Makefile for an application, which can be build in two different ways. One (we can call it basic output), there is an output called a.out1. Second output is made by explicitly passing argument to make - e.g. `make a.out2' and enables some features, which are turned on by preprocessor in sources. Thus object files are different than object files from a.out1. Is there an option to specify in Makefile when building a.out2, to explicitly say that if a.out1 is already build, clear it with object files and build a.out1 (and depended objs)? (and of course vice versa) thanks
Upvotes: 1
Views: 1253
Reputation: 99094
If you don't mind having separate object files (e.g. objA1.o
and objA2.o
), then here's a way to do it:
OBJECTS = objA objB objC
OBJ1 = $(addsuffix 1.o,$(OBJECTS))
OBJ2 = $(addsuffix 2.o,$(OBJECTS))
a.out1: $(OBJ1)
link $^ together one way
a.out2: $(OBJ2)
link $^ together another way
obj%1.o: %.cc
build $@ from $< by rule 1
obj%2.o: %.cc
build $@ from $< by rule 2
If the two executables (a.out
and a.out2
) need different object files, you can do this:
COMMON_OBJECTS = objA objB objC
OBJ1 := $(addsuffix 1.o,$(COMMON_OBJECTS))
OBJ2 := $(addsuffix 2.o,$(COMMON_OBJECTS))
OBJ1 += objD
OBJ2 += objE objF
If the difference between the two build commands (for building the objects in the two different ways) is something simple, like changing a compiler argument, you can make the last two rules a little simpler:
obj%1.o: CC_FLAGS += $(FLAGS_FOR_ONE)
obj%2.o: CC_FLAGS += $(FLAGS_FOR_TWO)
obj%1.o obj%2.o: %.cc
build $@ from $< using $(CC_FLAGS)
Likewise if the linking command is the same except for a linker argument (or exactly the same):
a.out1: $(OBJ1)
a.out1: LINKER_FLAGS += $(L_FLAGS_FOR_ONE)
a.out2: $(OBJ2)
a.out1: LINKER_FLAGS += $(L_FLAGS_FOR_TWO)
a.out1 a.out2: $(OBJ1)
link $^ together using $(LINKER_FLAGS)
Upvotes: 1
Reputation: 3730
How about this?
a.out2: clear1
#other commands
a.out1: clear2
#other commands
Upvotes: 0