CODEWITHSUNDEEP
system-verilog
maor shariki
maor shariki

Reputation: 15

System verilog throughout usage

I'm trying to code the following:

let's say that X is a bool term, and Y is a sequence, I would like to have a property saying that (X throughout Y) |-> term_to_check

meaning: if you see that term X holds for the entire Y sequence, then at the end of the sequence check some term. the problem is I'm not sure whether the above writing will check the term at the end of the sequence or during it.

any ideas how to code the described behavior?

Upvotes: 0

Views: 68

Answers (1)

dave_59
dave_59

Reputation: 42738

By using the overlapping implication operator |->, the term_to_check is checked in the same clock cycle that sequence Y ends. If you want it to check in the cycle following the end of the sequence, you could use the non-overlapping implication |=>, but my preference is always using the overlapping operator with |-> ##1.

Upvotes: 1

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