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scalasystem-verilogchisel
Nickolay Bandurin
Nickolay Bandurin

Reputation: 11

Scala Chisel. BlackBox with 2-d verilog ports

In my scala chisel project I need to insert system-verilog blackbox with 2-d arrays of ports. For example:

module something_bb(
  input  [`somtething_width-1     :0] something_i      [`somtething_num-1    :0],
  output [`somtethingelse_width-1 :0] somethingelse_o  [`somtethingelse_num-1:0]
)

---
endmodule

Can you tell me the easiest way to do it?

Upvotes: 0

Views: 187

Answers (1)

Kevin Laeufer
Kevin Laeufer

Reputation: 146

Unfortunately that is not supported by Chisel. You will have to write a Verilog wrapper, that exposes your 2D ports as 1D ports and then instantiate the wrapper as a Chisel blackbox.

Upvotes: 1

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