CODEWITHSUNDEEP
riscvrocket-chip
sammy17
sammy17

Reputation: 65

How to enable performance counters in Rocket Core

I am trying to enable performance counters in the Rocket core. I don't see the implementation of mhpmevent3, mhpmevent4, mhpmcounter3, mhpmcounter4 in the RTL of the defaultConfig. I see that following parameter is set to true by default but none of the mentioned counters does not get generated in the defaultConfig.

haveBasicCounters: Boolean = true

https://github.com/chipsalliance/rocket-chip/blob/b503f8ac28a497b2463ffbac84bfe66533ace0bb/src/main/scala/rocket/RocketCore.scala#L37

Can someone please explain how to enable these basic performance counters in Rocket?

I tried increasing nPerfCounters: Int = 0 to 8 and using following code to configure and read hpmcounter3. But counter never changed, it had a random value in each run.

addi x14, zero, 0x04
slli x14, x14, 8
addi x14, x14, 2
csrrw zero, mhpmevent3, x14 
...
csrr x28, mhpmcounter3 #Read counters in two different places
...
csrr x28, mhpmcounter3

I am using the configuration mentioned in https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf#page=16 3.11 as suggested in rocket-chip github issues.

Upvotes: 0

Views: 404

Answers (1)

ncppd
ncppd

Reputation: 55

In order to read perf counters from U-mode, be sure that you have correctly setup the mcounteren and scounteren CSRs, which enable reading perf counters from M->S mode and S->U mode respectively. Those two counters are 32-bit wide, and control the cycle, time, instret and hpmcounters3-31 CSRs. Setting the N bit to 1 of the mcounteren/scounteren enables the delegation of the corresponding N counter to the next (less) privileged mode.

Also make sure that the mcountinhibit CSR is correctly set. This CSR starts/stops perf event counting, and it may be the reason that you see a fixed reading every time.

Finally, you should try to change csrr x28, mhpmcounter3 to csrr x28, hpmcounter3 (no m before the name of the counter).

Upvotes: 0

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