Assembly Op code question

Question

If I am creating an instruction set for an 8-bit computer, is it possible for me to have some instructions with 2 bit op codes and some instructions with 3 bit op codes? The values of each of the op codes will be different, of course.

I have 3 r type instructions that have an op code of 00 I have 3 i type instructions, with op codes 01,11, and 10 Could I then make an instruction with an op code 100?

Answer 1

An alternative tradeoff is to have a mode bit in the status register. You have only 4 instructions at a time, but you can write to that location in memory with say, a MOV-style (like 8086 family) instruction. See the 65C816 for (ab?)use of having many, many modes.

Answer 2

Sure. One of your 2-bit instructions will be an escape code into the 3rd bit. The bad news is that it doesn't help expand your opcode range very much on that scale. More effective on the order of a 4-bit opcode series that can escape up to 8-bit or somesuch...

Answer 3

Look at the thumb instruction set from arm, they show a nice opcode map which is related in some way to what you are saying. Or look for lsasim at github, where I invented my own instruction set, some instructions only need four bits of opcode to figure out what the instruction is some need 8.

I assume you are asking about 8 bit instructions? As Tom said you control the horizontal, you control the vertical you can do whatever you want. You wont get much out of the two bit opcides, maybe you have only two registers that support those opcodes, for example:

00riiiii  store pc relative, r = 0 means register r0, r = 1 means register r1 iiiii is sign extended and added to the program counter for the store address

01riiiii  load pc relative

at this point though you have completely consumed HALF of your opcode space if you limit yourself to a fixed 8 bit instruction set. you didnt specify what you were doing. continuing with my thought all of the 0xxxxxxx opcodes are now consumed you have to start the rest with a 1

1000ssddd  move rd to rs (assumes rs = r0 to r3 and rd = r0 to r7
1001ssddd  move rs to rd
1010ssddd  add rs=rs+rd
1011ssddd  sub rs=rs-rd

etc.

You can make up whatever you want. The key is it has to be something you can decode, this would be valid

100ss0dd some operation
100ss1dd another operation

but this would not:

100ss0dd some operation
100ss1dd another operation
10iiiiii branch to pc plus sign extended immediate

because you cannot uniquely decode the third instruction from the other two, when you see 10xxxxxx is it a branch? well not if bit 2 is a 0 nor if bit 2 is a 1.

The arm/thumb opcode tables are very well drawn in this regard, starting at the top you have the instructions with fewer opcode bits and more operand bits, you need to chose those first but understand they use a large portion of your opcode space. then you have longer opcodes with fewer operands.

Answer 4

If you want your opcodes to have varying lengths, then you have to make sure that no shorter opcode is a substring of a longer opcode. That is, if you have the two-bit opcode 01, and a three-bit opcode 010, how is your decoder going to tell the difference?

I'm assuming that you're trying to fit the opcode and the operands into a single 8-bit quantity and treat it like a record. So, for example, you might have the instruction 01000111 where the first two bits are the opcode, the next three bits are the first operand, and the last three bits are the second operand.

If you have two opcodes, 01 and 010, how does your decoder decide between these two interpretations?

 01 000 111 - opcode 01, two three-bit arguments
 010 00 111 - opcode 010, a two-bit argument, and a three-bit argument

If you really want opcodes with varying lengths, you need to reserve prefix strings for the longer opcodes. So you could have the two-bit instructions 00, 01, and 10, and all longer instructions start with 11.