CODEWITHSUNDEEP
cachingarmstm32cortex-m
Ilya
Ilya

Reputation: 1525

ARMv7-M Cortex-M7 Cache Policy: Inner vs Outer, internal SRAM and external SDRAM

Context: Cortex-M7 STM32F746 Disco, writing own RTOS. Implementing memory policies for different memory regions for threads.

I've been writing my own RTOS kernel for the sake of understanding how things work (successfully until this point), and got to the point where I assign memory access policies for my threads using memory protection unit (MPU), since I want a complex kernel with bells and whistles and data safety. I got to the point where I need to set inner and outer cache policies. So the question emerged natually, what exactly inner and outer cache policies are.

Obviously, I went for ARM documentation on Cortex-M7. Here is a piece from this page on cache:

These custom cache policies are further divided into inner and outer policies, and you can choose different policies for each one. The caches inside the processor respond to the inner policy settings. The outer policy is signaled on the memory bus. The outer policy is used by extra levels of caching that are implemented outside of the processor in the memory system. An example of this type of extra level of caching is a level 2 cache controller. However, Cortex-M7 also exposes the inner cache policy settings as external signals. As a result, a chip designer can apply the inner settings to an external level of cache. Changing the settings in this way is a chip-specific implementation feature. For more information about this feature, read the chip-specific documentation.

I'll be honest, I didn't understand it very much. I believe I lack some knowledge on cache, and documentation is written in a very dry language, which only causes more questions.

The caches inside the processor respond to the inner policy settings. The outer policy is signaled on the memory bus.

As far as I understand, the inner policy applies to cache inside the MCU between internal SRAM and core, while outer is applied to...what? What memory bus? External SDRAM? Also, the outer policy is "signaled". Funny choice of verb. Why is it signaled? What signals to where?

And further down it goes about a possibility of exposing inner policy to the outside, which is implementation-specific, which, I guess, for STM32 is controlled by System Control Block or Cache Maintenance core peripherals?

I would be grateful if someone "dumbed down" this with a little simpler language, so that I can make sure I understand how it works correctly. I'm familiar with general cache concepts, write-through, write-back, cache lines, hits and misses, allocation policies and so on, but no material I read ever covered outer and inner cache policies.

If I'm choosing policy for the internal SRAM memory region, then outer policy should not matter, is this correct?

If I'm choosing policy for the external SDRAM without external L2 cache controller (about the existence of which I learned from this very text, never knew such thing exists), then internal policies apply to external SDRAM? Or external? Because I do plan to use external SDRAM eventually.

Upvotes: 0

Views: 770

Answers (1)

0___________
0___________

Reputation: 67476

Cortex-M7 also exposes the inner cache policy settings as external signals. As a result, a chip designer ...

To use L2 cache in your RTOS you will need to design your IC too.

External cache controller in this context means "external to the core" not to the chip itself.

So, if you write the RTOS for STM32 uC you do not have to worry about the L2 as STM chip designers did not implement it in their uCs.

Upvotes: 1

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