CODEWITHSUNDEEP
makefile
prioa
prioa

Reputation: 79

Makefile and subdirectories

I'm struggling with the correct syntax of a makefile.

This is my folder structure:

project
│   Makefile
│   HERE SHOULD BE THE OUT FILE AFTER make command    
│
└───include
│      header.h
│   
│   
└───src
       function1.c
       function2.c

How must the makefile look to ensure correct results?

This is my current makefile:

SOURCES =   src/function.c  src/function.c  src/function.c


OBJECTS =   $(SOURCES:.c=.o)

CC  =   cc
RM  =   rm -f
CFLAGS  =   -Wall -Wextra -Werror
NAME    =   output.a

all:    $(NAME)

$(NAME):
    $(CC)   $(CFLAGS)   -c  $(SOURCES)
    ar  rcs $(NAME) $(OBJECTS)

clean:
    $(RM)   $(OBJECTS)

fclean: clean
    $(RM)   $(NAME)

re: fclean  $(NAME)

my current output if i run make all:

cc      -Wall -Wextra -Werror   -c      src/function1.c src/function2.c
ar      rcs     output.a   src/function1.o src/function2.o src/function1.o
ar: src/function1.o: No such file or directory
make: *** [Makefile:15: output.a] Error 1

if i run make flcean the output looks the following:

rm -f   src/function1.o src/function2.o
rm -f   output.a

So it doesn´t remove anything because the .o files are stored in the root, not the /src subdirectory

Upvotes: 0

Views: 75

Answers (1)

John Bollinger
John Bollinger

Reputation: 181834

I'm struggling with the correct syntax of a makefile.

Your makefile syntax is fine. In fact, your makefile is syntactically valid and reasonably well structured. It looks a lot better than many of the ones we see around here.

I guess what you're actually struggling with is that it doesn't work, even after you fix the weird disagreement between the source file list in the makefile itself and the actual source files on disk. But "doesn't work" is a pretty vague, though lamentably common, description. You would get better help, faster, by saying something along the lines of "the .o files are created in the top-level directory instead of in the src/ directory." (Which is exactly what I expect to happen, and as a result, the ar command will fail, and the clean target will not clean the .o files.)

You need to understand that make itself doesn't know much about building software. What it knows is how to match rules to patterns so as to execute associated recipes of shell commands. The particular kinds of patterns it matches and the built-in rules that come with it are oriented toward building software, but you can't expect it to go very far with anticipating what you mean. It, like any other computer program, will happily do what you say, instead, when that differs. In this case, it just runs the cc command with the arguments you specify, and cc will choose under those circumstances to put the .o files in the working directory.

From a stylistic and best-practices standpoint, it's best to write rules that build only their target file, unlike your rule for $(NAME) that attempts to build not just $(NAME) but also all the component object files. The object files would be better built according to their own rule or rules. Making the object files prerequisites of the rule for $(NAME) will ensure that they get built when needed. That will also allow for them to not be built when that is not needed. That variation on your rule would look like this:

$(NAME): $(OBJECTS)
        ar  rcs $@ $^

Note also that in the recipe, I have substituted automatic variable $@ for a repetition of the rule target name. That's good form, but not obligatory. I have also substituted automatic variable $^ for a repetition of the prerequisite list. That's less clear-cut, in part because $^ is specific to GNU make, but if you're ok with that dependency then it's a great way to avoid repeating yourself.

Now, about building the object files: you could write a pattern rule (GNU make only) or a suffix rule that builds an object file from a corresponding C source file, or you could even write a separate rule for each object file. But you don't actually need to do that. make comes with a built in rule that will serve your needs in that area just fine, so your best bet may be to not attempt to provide your own rule for that at all. That is: modifying the rule for $(NAME) as suggested above should be sufficient for successful building, supposing, again, that the contents of your SOURCES variable accurately reflect the source files you want to build.

Upvotes: 1

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