CODEWITHSUNDEEP
system-verilog
AmV
AmV

Reputation: 11

How to make this expressions dynamic?

I'm trying to make the following expression dynamic with respect to size:

localparam MAX_ALLOWED_RD = 32'b1 << WIDTH_min;

The problem here is that if WIDTH_min becomes 32, the param becomes 0. What I'm trying to replace 32`b1 with something similar to "sizeof (WIDTH_min)"

How do I write this in SystemVerilog?

I have tried the following but get "'A_SIZE' is not a constant"

logic [WIDTH_min : 0] A_SIZE = 'b1; localparam MAX_ALLOWED_RD = A_SIZE << WIDTH_min ;

Upvotes: 0

Views: 206

Answers (2)

AmV
AmV

Reputation: 11

I was able to achieve it by doing the following:

localparam [WIDTH_min : 0]  WIDTH_min_size = '1;
localparam MAX_ALLOWED_RD     = WIDTH_min_size << ID_WIDTH_min ;

(I probably should have framed the question better.)

Upvotes: 0

G. C.
G. C.

Reputation: 427

The problem here is that the localparam is, by default, an integer, so its width is 32 bit [31:0].

So when you do this assignment:

 localparam MAX_ALLOWED_RD     = 32'b1 << WIDTH_min;

you would need 33 bits to assign that. You could solve this by using the width as parameter:

localparam WIDTH_min = 33;
localparam [WIDTH_min:0] MAX_ALLOWED_RD     = 32'b1 << WIDTH_min;

A_SIZE must be a parameter or localparam, not logic array.

Upvotes: 0

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