CODEWITHSUNDEEP
implementationvivadosynthesis
Arun Kumar
Arun Kumar

Reputation: 9

Why my simulation and post synthesis simulation results are different in vivado?

I simulated the rtl code and got the desired output, but when I run the post synthesis functional simulation, I see some random signals in the simulator screen and getting wrong output.

This is my first project in hardware and facing many issues in the process.

Upvotes: 0

Views: 1299

Answers (1)

ARude
ARude

Reputation: 65

There are many possible reasons why you are getting a different simulation result. But first it is important to understand what the differences between a behavioral and a post-synthesis simulation are.

Behavioural simulation only simulates the functional behavior of your RTL. Post-synthesis simulation happens with a synthesized netlist. During synthesis there is a lot a potential processing and optimization happening that can lead to a significantly different outcome compared to the behavioral simulation.

In the end, the post-synth simulation is the one that you should care most about, because the synthesized netlist will be passed to the next steps and eventually be placed and routed in the FPGA.

You very likely have some constructs or behavior that you are not very clear about. I suggest you take a look into the netlist to figure out if some functionality is actually missing, which is a hint that something got optimized away.

Upvotes: 0

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