BigTuna
BigTuna

Reputation: 101

Ampere Constant Memory and Read-Only Cache

I am trying to figure out the Ampere memory hierarchy. Details are fairly consistent down to the L1 / Shared Memory in the SM, but descriptions become confusing for notions of constant memory and the read-only cache.

In Pradeep Gupta's blog, https://developer.nvidia.com/blog/cuda-refresher-cuda-programming-model/, he provides the following architectural picture:

Test

The figure shows the notion of the Read-Only memory separate from the L1/Shared Memory, and in his text he states the following:

"Read-only memory — Each SM has an instruction cache, constant memory, texture memory and RO cache, which is read-only to kernel code."

For Ampere, is there still a constant memory, if so how big is it? Is it still 64KB, tailorable or other? I assume this is for data defined as __const__ in the code. What other data is in the "RO cache" noted above? Also, I thought I read that texture memory had been collapsed into the L1/Shared Memory space, is this not true?

I appreciate any insight that can be provided.

Upvotes: 1

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