When does the CPU execute an interrupt service routine?

Question

I have a question like that:

When does the CPU execute an interrupt service routine?

a) After the instruction decoding phase, before the instruction execution phase
b) After completion of the last phase of order execution
c) After the fetching phase, before the decoding phase of the currently processed instruction
d) After completion of the order execution phase, before the next order download phase

I think the right answer is c) but I cannot find any confirmation

Answer 1

The answer to this question is the implementation details of your CPU. Every company can use their own favourite mechanism. It does not matter how the CPU internally implements this. Only the designers of your CPU can tell you how they have implemented the ISR mechanisms. Typically the instruction pipeline is much longer and more complex than what you wrote. There are also things like branch prediction, speculative execution or the caching.

All this must be in a way, that is invisible for the user. Everything what the user can trust is the assembler code. And that logical level is very simple: An instruction is either executed or it is not executed. All the CPU internals and the whole instruction pipeline gives you this guarantee at any time.

This is also valid if an ISR is to be executed. The ISR will start between two CPU instructions. That means the CPU instruction before the interrupt comes will be logically completed and the CPU instruction that comes next will not be started, regardless of where in the pipeline it is already. It can even happen that the instruction has been passed the execution phase out of order in a speculative way and the results are only kept back until the previous instruction is completed. If in this situation an ISR comes, these results are dropped.

So the question cannot be "What happens with the instruction pipeline?" The question is rather "What happens with the current instruction when an interrupt occurs?". Because I said, the ISR is started between two instructions. So we must clarify between which two instructions. Is the current instruction dropped or completed before an ISR is started?

The specification of the Intel i486 for example is very clear. "The processor only responds to interrupts between instructions, (REPeat String instructions, have an "interrupt window", between memory moves, which allows interrupts during long string moves)". This answers your question. The current instruction is completed.

Technically (as can also be read in the specification of the Intel i486) an interrupt is not only a signal that is raised on an interrupt pin. In order to accept an interrupt, the processor generates an Interrupt Acknowledge. And there again, the specification clarifies, that this happens "between instructions". The CPU specifications do not not give you more information.

That means answer c) is wrong. The correct answer is: The current instruction is completed. Then the processor flushes the pipeline and reacts to the interrupt. This is how the Intel i486 does it. This does not mean that other processors do it in the same way.