CODEWITHSUNDEEP
armcortex-m
Chandan Gupta
Chandan Gupta

Reputation: 13

ARM cortex M4 interrupt handling when interrupts are disabled

In a ARM cortex M4 processor, how does NVIC handles interrupts if the interrupts are disabled?

Eg: Lets say, core receives a UART RX interrupt and enter the ISR. In the ISR, first we disable all interrupts, do some work, enable all interrupts.

What happens if another interrupt occurs during the time interrupts were disabled? Does NVIC still set the interrupts pending flag for the new interrupt?

Upvotes: 1

Views: 810

Answers (1)

Tom V
Tom V

Reputation: 5510

Yes, an interrupt can be pending when it is disabled. It will remain that way until interrupts are enabled or it is cleared.

If the first interrupt is in a lower priority group than second, then the second one will pre-empt the first one as soon as you re-enable it and you will be in a nested interrupt state.

Otherwise, if the second interrupt is in the same or lower priority group, it will be chained. This is a hardware feature where the main context is not restored but execution jumps straight from the end of one interrupt to the start of the next, reducing latency to just the number of cycles required to fetch and decode the next instruction.

Upvotes: 1

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