CODEWITHSUNDEEP
assemblymipspipelinecpu-hazard
Shivam Singh
Shivam Singh

Reputation: 49

I am confused as to which instructions in MIPS have a hazard

I have been looking at this problem, and upon my own attempt, I found 3 data hazards. However, other sources say otherwise.

Find all hazards in the following instructions (MIPS Pipeline):

add $t3, $t1, $t2
sub $t3, $t2, $t1
and $t4, $t3, $t1
or $t0, $t3, $t4
xor $t1, $t4, $t3
sw $t4, 4($t0)

Not only that, but even chatGPT isnt giving any conclusive explanations:

Upvotes: 0

Views: 517

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26646

This is a contrived and silly code sequence.

add $t3, $t1, $t2
sub $t3, $t2, $t1

In the above, $t3 is written by add but then overwritten by sub and without the adds $t3 being ever used.  In and of itself, this does not create a hazard, the data hazards are also known as RAW Hazards, which stands for Read After Write.  In the above, there is only Write After Write, for which MIPS pipelines do not suffer a hazard.

In the next instruction:

and $t4, $t3, $t1

there is one data RAW hazard, on $t3.

When we factor in the next instruction:

or $t0, $t3, $t4

We have two hazards in one instruction, one on $t3 and one on $t4.  Since there are two hazards in one instruction, we have to become problem-statement reading experts to determine the answer.  As it is still only one instruction, if you're counting instructions that have hazards, it counts as one, but if you're counting hazards themselves, it counts as two.

With:

xor $t1, $t4, $t3

We have a hazard on $t4, but $t3 has made it through the pipeline and back to the register file, if you use the common implementation detail that the register file can read current-cycle-written results.

And finally:

sw $t4, 4($t0)

has a RAW data hazard on $t0.

So, I count 5 RAW hazards, and, 4 instructions that have at least one RAW hazard.

Upvotes: 0

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