CODEWITHSUNDEEP
timerembeddedcomparestm32f4stm32cubeide
Ariarikta
Ariarikta

Reputation: 1

TIMx CHx in Output Compare Mode using STM32F4 series and Configuring CubeMx

I want to configure a CHx (could be CH1, CH2, CH3 or CH4) of a particular timer TIMx in the output compare mode. I want to utilize the CCRx (Capture/Compare Register of that individual channel) to generate pulses.

The main reason for using CCRx is to gain control on the Ton period of the generated pulses as my goal is to target a particular duration on the Ton period.

The only part which is confusing to me is to understand the calculations for Prescaler, ARR (32 bit) and Pulse (32 bit value).

I would kindly like to understand how these values are calculated and I know some values are supposed to e assumed. I referred a lot of materials but always end up getting stuck in the formulas as there are a wide variety of them.

I was able to generate output pulses for 10 microseconds with the following configuration: My SYSCLK is running @100 MHz APB1/APB2 = 100 MHz Prescaler (PSC) = 9, Period (ARR) = 99, Pulse = 0

But when I verified the reason behind selecting the values using the formulas and concept available on the web, I noticed they values never tally with the results.

I tried varying the Pulse value, but it doesn't affect the pulse duration unless I change the PSC value. I want to configure multiple channels in OC mode and in that case, I want to keep the PSC value untouched and only vary the Pulse value associated with individual Channels to gain control on their respective pulse duration of the output generated pulses.

Your advices would be kindly appreciated.

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Edit 1:- I did the following calculations

To achieve a continuous pulse for a duration of 10 microsec. I referred the following calculation.

Prescaler Output (CNTx_CLK) = (TIMx_CLK) / (PSC+1)

My SYSCLK = 100MHz As I want to generate output pulse for 10 microsec., The timer clock frequency would be = 1/10microsec. = 100KHz or 100,000 Hz.

Based on the above formula,

100 KHz = 100 MHz/(PSC+1) So, PSC = 999.

Now, I also came across a formula to calculate the ARR value after finding the PSC value. (ref:- Programming STM32 book)

ARR = [(fxi)/(PSC+1)] - 1, where f = SYSCLK (100 MHz), i = the desired pulse duration (10 microsec.), we have the PSC = 999 Which results in ARR = 0.

This is where I am getting stuck at the moment.

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Edit 2:- To generate an output pulse train of Ton = 1 us, I was able to correctly calculate the Period (ARR) and Prescaler value with the following formulas:-

I initially used a PSC = 9 and with the formula -> ARR = [(SYSCLK * Interval)/(PSC+1)] - 1. I got ARR = 9, resulting in the Pulse width of 1 us (Ton = 1us).

Note:- I am still not loading any value in the Pulse field of particular channel I have configured in OC mode.

But, now, if I want to configure another channel, for instance CH2, in OC mode and generate a pulse train of duration, for instance, 1 ms, then how should I make it work? I have already configured the PSC and ARR to generate a pulse of 1 us on CH1.

Upvotes: 0

Views: 820

Answers (1)

wek
wek

Reputation: 1213

As @pmacfarlane already said in comments, (TIMx_ARR + 1) determines PWM period, TIMx_CCRx deterimines pulse lenght (thus together they determine duty ratio), and both are multiplied by (TIMx_PSC + 1) which thus determines granularity i.e. the timing step in which both period and pulse length can be adjusted. Generally, you want to keep TIMx_PSC as low as possible, but that is limited by the fact that most STM32 timers are 16-bit (exceptions are generally TIM2 and TIM5). For example, with your 100MHz timer clock, the maximum period in a 16-bit timer is 655.35us; if you want longer period, you need to increase PSC accordingly.

There is only one counting element in each timer, so period of all four channels of one timer is always the same, only their pulse length can be individually set. In other words, you cannot generate PWM with different frequencies from different channels of one timer.

Also, in 'F4 timer, you also cannot generate PWM on different channels with random phase shift, one of the pulses edges is always aligned together on all channels, as it's generated by the Update event (overflow); or in up-down mode the middle of all pulses is aligned together (newer STM32 models do have modes where this limitation can be circumvented).

Upvotes: 1

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