How does PCIe's flow control avoid overflows with in-flight packets?

Question

So PCIe has this mechanism where a receiver will advertise a certain amount of credits to the transmitter, that way the transmitter can check if the data that to be sent can fit in the receiver's buffer.

I don't understand how a mechanism like that can work when you take into account the inherent latencies of a physical implementation.

Imagine this: 1 - receiver advertises 3 credits 2 - transmitter sends a packet taking up 1 credit. 3 - at the same time, an extra credit becomes available in the receiver (the application layer has consumed some data), so the receiver advertises 4 credits. 4 - the transmitter receives the advertisement for 4 credits right after the packet is sent, so it stores it as the current available credits in the receiver. 5 - The packet makes it all the way to the receiver, so the now the receiver has 3 credits available.

At this point receiver and transmitter are out-of-sync, and an overflow might happen. I assume that to avoid this there must be a way of knowing what was the last packet the receiver got before sending the flow control message, yet I don't really see a sequence number in the DLL packets that are used for Flow control.

Does anybody understand how this actually works?