CODEWITHSUNDEEP
system-verilogsystem-verilog-assertions
Rupert Swarbrick
Rupert Swarbrick

Reputation: 2803

Negating a sequence in SystemVerilog assertions

I have a reasonably basic SVA question, but I'm not sure what the trick is for getting somewhere. I'm trying to say that if A is true for 32 cycles, then B should become true at some point. Equivalently, I could say A && !B is not allowed to be true for 32 cycles.

Is there a way to encode this as a SystemVerilog assertion? I'm in an FPV context, so it would also be really nice to avoid encoding "not xyz" as xyz |-> 0 (to avoid the tool reporting a hole in the coverage).

Upvotes: 0

Views: 138

Answers (1)

Rupert Swarbrick
Rupert Swarbrick

Reputation: 2803

Well, that was easier than I feared! It turns out that you can negate properties with a not operator. So the example above turns into something like not ((A && !B) [*32]).

For the original context for the question, see OpenTitan PR #22528.

Upvotes: 0

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