CODEWITHSUNDEEP
system-verilogflip-flop
Jingle Jangle
Jingle Jangle

Reputation: 19

How do you count the number of flip flops created in an always_ff statement?

Is there an algorithm I can apply to determine this? If so, what is it?

Here is an example you can use to illustrate:

logic Out;
logic [7:0] Count;

always_ff @(posedge Clock or posedge Reset)
begin
   if (Reset)
      Count = 0;
   else
      Count = Count + 1;
   Out <= Count[7];
end

Upvotes: -1

Views: 62

Answers (1)

Mikef
Mikef

Reputation: 2508

Consider what you are modeling.

You have

  • An 8 bit counter which uses 8 FF's
  • A single FF creates a delayed version of bit [7] to Out.

9 FFs' here

There is no single simple algorithm for analyzing the utilization of FPGA resources based on the RTL code.

For simple designs just add up what you are modeling.

For very large designs use the synthesis tool to get the utilization of various resources.

If its a mid sized design use your judgment which approach is easier.

If you need accurate numbers on anything except something trivially small (like this) use the tool; the tools will do some unexpected things from the user point of view until you have experience with the tricks, which depend on the tool and the part targeted.

The tool may target FF's (logic fabric), BRAM, or SRL's with relatively small changes to the code like the existence/non-existance of reset, or the type of reset (synchronous or asynchronous). That is why by bias is toward using the synthesis tools.

Its useful to predict the utilization using your understanding of whats modeled, then compare to what the tool did. If they different then some investigation is necessary.

Upvotes: 0

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