CODEWITHSUNDEEP
assemblymipsriscvvitis
Harry Betts
Harry Betts

Reputation: 1

Converting ARM assembly to RISC-V assembly

I am trying to rewrite this code. It works perfectly for ARM assembly, but I am trying to rewrite it in RISC-V assembly. Here is the ARM code:

.text
.global main

.equ ADD1, 0x40000000
.set ADD2, 0x40000004

main:
    ldr r1,=ADD1
    ldr r2,=ADD2
loop:
    ldr r0,[r1]
    str r0,[r2] 
    b loop      

.end

My best attempt is:

.global main

.data
ADD1: .word 0x40000000
ADD2: .word 0x40000004

.text
main:
    la  t0, ADD1 
    lw  a1, 0(t0)    
    la  t1, ADD2     
    sw  a1, 0(t1)    
    j main           

.end

But when I try and build it in Vitis, I get the following errors:

../src/PROJ1.S:9: Error: register expected, but saw 't0,ADD'
../src/PROJ1.S:9: Error: register expected, but saw '0,ADD1'
../src/PROJ1.S:9: Fatal error: missing operand
make: *** [src/subdir.mk:23: src/PROJ1.o] Error 1

I cannot seem to find any assistance for the first two errors. How do I fix all of these particular issues?

Upvotes: 0

Views: 192

Answers (1)

Harry Betts
Harry Betts

Reputation: 1

The toolchain you have used is not the correct one for this particular version of Assembly.

On Vitis Classic: Right click on the application icon, go into C/C++ settings and change the toolchain to the correct assembly language.

Upvotes: 0

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