CODEWITHSUNDEEP
vhdlsynthesis
Philippe
Philippe

Reputation: 3730

Does the synthesizer care about one or two processes?

There are two popular ways of coding a state machine in VHDL: one process or two processes. There are rumors (and it is taught in some colleges) that two processes might result in better hardware. Does anybody have any hard evidence for this? My own preliminary tests show that there is no difference at all.

I'm looking for reproducible experiments: VHDL code for the two coding styles, and specifics on how to synthesize them (which tool, which parameters).

Please help me to either debunk or confirm the myth that two processes result in better synthesized hardware.

Upvotes: 5

Views: 603

Answers (3)

user597225
user597225

Reputation:

The code below should demonstrate this for libraries that have clock gates. The simulation results will be the same and Formal Verification will prove both of these identical. However the first one will likely use less power and less area.

//Instances 1 clock gate
reg [7:0] value;
always @(posedge i_clk)
  if(enable)
    value <= new_value; 

//Instances 8 muxes
always @(posedge i_clk)
  if(enable)
    value <= new_value;
  else //Exhaustive so assignment always occurs
    value <= value;

The first example will use a single clock gate for the clock into all eight DFFs. The second example will use 8 muxes looping back the output from each DFF to it's input. Depending on the area and power ratio of clock gates to muxes, the differences can be significant. This was tested on Talus.

Of course the else clause in the second example is useless but the point of the experiment was to see how well the tool handled complex casez/x statements and shared enables across always blocks. For FSMs, I would lean towards syntax doesn't matter as long as the FSM is detected. I base this on how XST handles them and that state machine optimization is a very mature topic.

Upvotes: 0

Paul S
Paul S

Reputation: 7755

A lot of this kind of "knowledge" is based on the tools that were around 20 years ago. Things have moved on.

That's not to say that it's everything has been fixed in all cases, but you're doing the right thing by actually performing trials.

Other things which have been avoided in the past are:

  • Generics, because apparently they're unsynthesizable. Not true, and far better than
    pre-processing code, which is the normally what's being defended.
  • Records on ports. This did cause DC-shell problems for a long time. It would misconnect things. I don't know if this is solved.
  • Various styles of synchronous process, especially those using wait rather than the sensitivity list. This one is particularly crazy because if you read the VHDL spec it says the two are equivalent and should be implemented in the same way.

Upvotes: 3

Martin Thompson
Martin Thompson

Reputation: 16822

Sorry, no reproducible experiment, but I'd be staggered if a synthesizer cared (at least these days - I have no hard evidence though)! Surely it just parses the VHDL down to a bunch of logic feeding a bunch of flipflops.

I don't even know if it used to be a problem with old-fashioned synthesizers or whether people just assumed it to be so!

Upvotes: 2

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