CODEWITHSUNDEEP
system-verilogquestasim
Sharafat Hussain
Sharafat Hussain

Reputation: 29

coverpoint at_least option is not catching in simulator causes missing of bins

I am writing a cross coverpoint for a unique case where I have to set option.at_least=0.

    test_atleast_cp: cross signal_a_1bit, signal_b_1bit {
      option.at_least = 0;
    }

I am expecting that all the 4 bins are 100% covered for this this cross but the questa visualizer shows the following

enter image description here

I am using Questa tool for simulation // Questa Sim-64 // Version 2024.2 linux_x86_64 May 20 2024

Upvotes: -1

Views: 54

Answers (1)

dave_59
dave_59

Reputation: 42738

The IEEE 1800-2023 SystemVerilog LRM is not clear about the behavior of setting the at_least counter to 0. In most other places, setting a counter limit to 0 means don't count or unlimited. Try setting the option weight to 0 instead.

Upvotes: 0

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