CODEWITHSUNDEEP
qemuarm64hypervisor
Daniel Rossier
Daniel Rossier

Reputation: 1

QEMU/virt64 vGIC dist and CPU interface addresses

I'm working with QEMU/virt64 (armv8) and I've a question related to an IRQ injection from my hypervisor running in EL2 mode. First, is it correct that the vGIC distributor address is 0x08000000, i.e. the same than the physical GIC, and the CPU interface address is 0x08040000 ? When I've populated LR registers with pending IRQ (actually only one, SGI #4), I'm setting the hcr_el2 register with HCR_VI bit to emulate the CPU IRQ assertion, and when I switch to the guest (running in EL1), I'm dropping in the exception as expected, but I'm reading IRQ 1023 from the GIC continuously... I've the impression that I'm not using the right addresses (which are obviously mapped in the hypervisor via the 2nd-stage translation).

Any idea?

Upvotes: 0

Views: 59

Answers (1)

Peter Maydell
Peter Maydell

Reputation: 11493

The location of the memory mapped components of the GIC is platform dependent. This means that for the physical interfaces it depends on the machine, and the OS needs to either (a) know what hardware it is running on and hardcode it or (b) have some data driven mechanism (typically either DTB or ACPI tables) which tells it the right address.

For a guest running under a hypervisor, the hypervisor can map its emulation of the memory-mapped parts of the GIC wherever it likes -- it just has to ensure that it and the guest agree about this. (For instance the hypervisor might model a known piece of hardware that the guest thinks it's running on, or it might arrange with the VMM to ensure that the guest gets passed DTB/ACPI info telling it where the GIC memory mapped components are).

For a hypervisor like KVM, where the "virtual machine management" part is in userspace, KVM provides an API so the VMM can tell it "put the VGIC distributor at this address", because the VMM controls the memory map the guest sees.

(You don't say if you're using GICv2 or GICv3 here, but the basic idea is the same: some bits of the GIC the guest sees are provided by the hardware, some must be emulated by the hypervisor, the hypervisor gets to pick where they live in the guest's memory map, the hypervisor and guest need to agree about that memory map the same way they need to agree about where the UART lives and where the RAM is.)

Upvotes: 0

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