CODEWITHSUNDEEP
system-verilog
Moberg
Moberg

Reputation: 5519

Detect shape mismatch in packed dimensions in assignment

System verilog allow multiple packed dimensions for a signal. But what is the defined behavior is a signal with shape 2x3 is assigned from another one shaped 3x2? The total amount of bits is the same but the simulation seems to gladly accept this kind of assignment.

Example:

module test();
   wire [1:0][2:0] x;
   assign x[0][0] = 1;
   assign x[1][2] = 1'dx;
   wire [2:0][1:0] y;
   wire [5:0] z;

   assign y = x;       // <-- Would like an error or lint error to occur
   assign z = x;       // <-- Would like an error or lint error to occur

   wire [2:0][1:0] w;
   assign w = 6'd63;   // <-- Would like an error or lint error to occur

   initial $display("FOOOOO %06b %06b %06b %06b", x, y, z, w);
endmodule

Both vcs, questa and verilator runs this code without emitting any warning or error. Can they be configured to detect this as an error? Is there some other linter tool available?

Upvotes: 1

Views: 54

Answers (2)

dave_59
dave_59

Reputation: 42748

SystemVerilog inherited Verilog's weak integral packed types. The LRM specifically allows assignments from one integral type to another without any warnings. Some tools have added warnings for size-mismatches where truncation or extension is needed. But if the integral packed types are the same size, it's perfectly normal for the assignment as a whole to happen without any warnings. The difference in packed dimensions types provides alternative slicing mechanisms.

Unpacked arrays and structs in SystemVerilog are strong types. You could wrap your integral type inside an unpacked struct to get your intened behavior

typedef logic [1:0][2:0] ul2x3_t;
typedef logic [2:0][1:0] ul3x2_t;
typedef struct {ul2x3_t value;} ul2x3_s;
typedef struct {ul3x2_t value;} ul3x2_s;

wire ul2x3_s x;
wire ul3x2_s y;

assign x = y; // this would be a compile error
assign x.value = y.value + 1; // this is legal. 
assign x = ul2x3_s'(y.value + 1); // illegal because addition is 32-bits
assign x = ul2x3_s'(y.value + 6'b1); // legal

Using Strong Types in SystemVerilog Design and Verification Environments

Upvotes: 2

Justin N
Justin N

Reputation: 911

That's defined behavior for packed arrays and is allowed by the standard. If you want array size checking, you can use unpacked arrays.

Here's the relevant section of the standard:

For the purposes of assignment, a packed array is treated as a vector. Any vector expression can be assigned to any packed array. The packed array bounds of the target packed array do not affect the assignment. A packed array cannot be directly assigned to an unpacked array without an explicit cast.

Upvotes: 1

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