Godspped
Reputation: 743
Arduino Due integration with FreeRTOS running into hard faults on simple led toggle through a task
I am trying to integrate FreeRTOS into Arduino Due (Atmel CM3 3X8E) without using Arduino IDE. I have a simple blinking application working without FreeRTOS so I know my reset handler is working but when I try to add FreeRTOS I am running into a hard fault. Does anyone know what I am doing wrong, I have attached my code here:
main.c
#include <stdint.h>
#include <stdio.h>
#include <stdarg.h>
#include "FreeRTOS.h"
#include "task.h"
#include "core_cm3.h"
/* ID PIOB in PMC */
#define ID_PIOB (12U)
TaskHandle_t taskHandle;
void LED_Task()
{
PMC->PMC_PCER0 = (1 << ID_PIOB);
// Configure PIOB pin 27 as output
PIOB->PIO_PER = (1 << 27); // Enable PIO control
PIOB->PIO_OER = (1 << 27); // Enable output
while (1)
{
PIOB->PIO_SODR = (1 << 27);
vTaskDelay( 500 );
PIOB->PIO_CODR = (1 << 27);
vTaskDelay( 500 );
}
vTaskDelete(NULL);
}
int
main(void)
{
PMC->PMC_PCER0 = (1 << ID_PIOB);
PIOB->PIO_PER = (1 << 27);
PIOB->PIO_OER = (1 << 27);
xTaskCreate(LED_Task, "LED Task", 1024, NULL, 3, &taskHandle);
vTaskStartScheduler();
return 0;
}
startup_sam3xa.c
#include "sam3xa.h"
#include <stdio.h>
#include <stdarg.h>
#include <sys/types.h>
#include <sys/stat.h>
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
extern int main(void);
extern uint8_t _sheap; // Start of heap from linker script
extern uint8_t _eheap; // End of heap from linker script
static uint8_t *heap_end = &_sheap;
void *_sbrk(int incr) {
uint8_t *prev_heap_end = heap_end;
if ((heap_end + incr) > &_eheap) {
// Out of heap memory
return (void *)-1;
}
heap_end += incr;
return (void *)prev_heap_end;
}
/* Default empty handler */
void Dummy_Handler(void)
{
while (1) {
}
}
/* Cortex-M3 core handlers */
void NMI_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void MemManage_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void SUPC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void RSTC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void RTT_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void PMC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void EFC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void UART0_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void UART1_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void PIOA_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void PIOB_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void TWI0_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void TWI1_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void SPI_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void DACC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void PWM_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
void USART0_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
/* Reset handler: Initialize data and bss sections */
extern uint32_t _srelocate, _erelocate, _sfixed, _szero, _ezero;
void Reset_Handler(void) {
uint32_t *pSrc, *pDest;
/* Copy .data section to RAM */
pSrc = &_sfixed;
pDest = &_srelocate;
while (pDest < &_erelocate) {
*pDest++ = *pSrc++;
}
/* Zero .bss section */
pDest = &_szero;
while (pDest < &_ezero) {
*pDest++ = 0;
}
/* Call main */
main();
/* Infinite loop */
while (1);
}
void Default_Handler(void)
{
while (1) {
}
}
void _exit(int status) {
(void)status;
while (1) {
}
}
extern void xPortSysTickHandler( void );
/* Exception Table */
__attribute__ ((section(".isr_vector")))
const DeviceVectors exception_table = {
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) MemManage_Handler,
(void*) BusFault_Handler,
(void*) UsageFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) DebugMon_Handler,
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) xPortSysTickHandler,
/* Configurable interrupts */
(void*) SUPC_Handler, /* 0 Supply Controller */
(void*) RSTC_Handler, /* 1 Reset Controller */
(void*) RTC_Handler, /* 2 Real Time Clock */
(void*) RTT_Handler, /* 3 Real Time Timer */
(void*) WDT_Handler, /* 4 Watchdog Timer */
(void*) PMC_Handler, /* 5 PMC */
(void*) EFC_Handler, /* 6 EEFC */
(void*) (0UL), /* 7 Reserved */
(void*) UART0_Handler, /* 8 UART0 */
(void*) UART1_Handler, /* 9 UART1 */
(void*) (0UL), /* 10 Reserved */
(void*) PIOA_Handler, /* 11 Parallel IO Controller A */
(void*) PIOB_Handler, /* 12 Parallel IO Controller B */
#ifdef _SAM3N_PIOC_INSTANCE_
(void*) PIOC_Handler, /* 13 Parallel IO Controller C */
#else
(void*) (0UL), /* 13 Reserved */
#endif /* _SAM3N_PIOC_INSTANCE_ */
(void*) USART0_Handler, /* 14 USART 0 */
#ifdef _SAM3N_USART1_INSTANCE_
(void*) USART1_Handler, /* 15 USART 1 */
#else
(void*) (0UL), /* 15 Reserved */
#endif /* _SAM3N_USART1_INSTANCE_ */
(void*) (0UL), /* 16 Reserved */
(void*) (0UL), /* 17 Reserved */
(void*) (0UL), /* 18 Reserved */
(void*) TWI0_Handler, /* 19 TWI 0 */
(void*) TWI1_Handler, /* 20 TWI 1 */
(void*) SPI_Handler, /* 21 SPI */
(void*) (0UL), /* 22 Reserved */
(void*) TC0_Handler, /* 23 Timer Counter 0 */
(void*) TC1_Handler, /* 24 Timer Counter 1 */
(void*) TC2_Handler, /* 25 Timer Counter 2 */
#ifdef _SAM3N_TC1_INSTANCE_
(void*) TC3_Handler, /* 26 Timer Counter 3 */
(void*) TC4_Handler, /* 27 Timer Counter 4 */
(void*) TC5_Handler, /* 28 Timer Counter 5 */
#else
(void*) (0UL), /* 26 Reserved */
(void*) (0UL), /* 27 Reserved */
(void*) (0UL), /* 28 Reserved */
#endif /* _SAM3N_TC1_INSTANCE_ */
(void*) ADC_Handler, /* 29 ADC controller */
(void*) DACC_Handler, /* 30 DAC controller */
(void*) PWM_Handler /* 31 PWM */
};
core_cm3.h
#ifndef __CORE_CM3_H__
#define __CORE_CM3_H__
/* ------------------ Includes ------------------ */
#include <stdint.h> /* Standard integer types */
/* ------------------ Processor and Core Peripherals ------------------ */
typedef struct {
volatile uint32_t ISER[8];
uint32_t RESERVED0[24];
volatile uint32_t ICER[8];
uint32_t RESERVED1[24];
volatile uint32_t ISPR[8];
uint32_t RESERVED2[24];
volatile uint32_t ICPR[8];
uint32_t RESERVED3[24];
volatile uint32_t IABR[8];
uint32_t RESERVED4[56];
volatile uint8_t IP[240];
uint32_t RESERVED5[644];
volatile uint32_t STIR;
} NVIC_Type;
typedef struct {
volatile uint32_t PIO_PER;
volatile uint32_t PIO_PDR;
volatile uint32_t PIO_OER;
volatile uint32_t PIO_ODR;
volatile uint32_t PIO_SODR;
volatile uint32_t PIO_CODR;
volatile uint32_t PIO_PDSR;
volatile uint32_t PIO_OER2;
} PIO_TypeDef;
/* Register structure for PMC (Power Management Controller) */
typedef struct {
volatile uint32_t PMC_SCER;
volatile uint32_t PMC_SCDR;
volatile uint32_t PMC_PCER0;
volatile uint32_t PMC_PCDR0;
} PMC_TypeDef;
#define SCS_BASE (0xE000E000UL)
#define NVIC_BASE (SCS_BASE + 0x0100UL)
#define SCB_BASE (SCS_BASE + 0x0D00UL)
/* Base addresses for peripherals */
#define PIOB_BASE (0x400E1000U)
#define PMC_BASE (0x400E0600U)
/* Peripheral instances */
#define PIOB ((PIO_TypeDef *)PIOB_BASE)
#define PMC ((PMC_TypeDef *)PMC_BASE)
/* Peripheral Register Structure Definitions */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
/* ------------------ System Control Block (SCB) ------------------ */
typedef struct {
volatile uint32_t CPUID; /*!< CPU ID Base Register */
volatile uint32_t ICSR; /*!< Interrupt Control and State Register */
volatile uint32_t VTOR; /*!< Vector Table Offset Register */
volatile uint32_t AIRCR; /*!< Application Interrupt and Reset Control Register */
volatile uint32_t SCR; /*!< System Control Register */
volatile uint32_t CCR; /*!< Configuration and Control Register */
volatile uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
volatile uint32_t SHCSR; /*!< System Handler Control and State Register */
volatile uint32_t CFSR; /*!< Configurable Fault Status Register */
volatile uint32_t HFSR; /*!< HardFault Status Register */
volatile uint32_t DFSR; /*!< Debug Fault Status Register */
volatile uint32_t MMFAR; /*!< MemManage Fault Address Register */
volatile uint32_t BFAR; /*!< BusFault Address Register */
volatile uint32_t AFSR; /*!< Auxiliary Fault Status Register */
volatile uint32_t PFR[2]; /*!< Processor Feature Register */
volatile uint32_t DFR; /*!< Debug Feature Register */
volatile uint32_t ADR; /*!< Auxiliary Feature Register */
volatile uint32_t MMFR[4]; /*!< Memory Model Feature Register */
volatile uint32_t ISAR[5]; /*!< Instruction Set Attributes Register */
uint32_t RESERVED0[5];
volatile uint32_t CPACR; /*!< Coprocessor Access Control Register */
} SCB_Type;
/* Peripheral Register Definitions */
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
/* ------------------ System Control Functions ------------------ */
/**
* @brief Enable global interrupts
*/
static inline void __enable_irq(void) {
__asm volatile ("cpsie i" : : : "memory");
}
/**
* @brief Disable global interrupts
*/
static inline void __disable_irq(void) {
__asm volatile ("cpsid i" : : : "memory");
}
/* ------------------ Inline Functions for NVIC ------------------ */
/**
* @brief Set priority for an interrupt.
* @param IRQn: Interrupt number
* @param priority: Priority to set
*/
static inline void NVIC_SetPriority(int32_t IRQn, uint32_t priority) {
NVIC->IP[IRQn] = (uint8_t)(priority & 0xFF);
}
/**
* @brief Enable an interrupt.
* @param IRQn: Interrupt number
*/
static inline void NVIC_EnableIRQ(int32_t IRQn) {
NVIC->ISER[IRQn >> 5] = (1UL << (IRQn & 0x1F));
}
/**
* @brief Disable an interrupt.
* @param IRQn: Interrupt number
*/
static inline void NVIC_DisableIRQ(int32_t IRQn) {
NVIC->ICER[IRQn >> 5] = (1UL << (IRQn & 0x1F));
}
/* ------------------ End of File ------------------ */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM3_H__ */
sam3xa.h
#ifndef SAM3XA_H
#define SAM3XA_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* CMSIS Definitions */
#ifndef __IO
#define __IO volatile
#endif
/* Base addresses for peripherals */
#define PIOA_BASE (0x400E0E00U)
#define PIOB_BASE (0x400E1000U)
#define PIOC_BASE (0x400E1200U)
#define SCB_VTOR_TBLOFF_Msk 0x1FFFFF80 /* Mask for vector table offset */
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnMemManage_Handler;
void* pfnBusFault_Handler;
void* pfnUsageFault_Handler;
void* pfnReserved1_Handler;
void* pfnReserved2_Handler;
void* pfnReserved3_Handler;
void* pfnReserved4_Handler;
void* pfnSVC_Handler;
void* pfnDebugMon_Handler;
void* pfnReserved5_Handler;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSUPC_Handler; /* 0 Supply Controller */
void* pfnRSTC_Handler; /* 1 Reset Controller */
void* pfnRTC_Handler; /* 2 Real Time Clock */
void* pfnRTT_Handler; /* 3 Real Time Timer */
void* pfnWDT_Handler; /* 4 Watchdog Timer */
void* pfnPMC_Handler; /* 5 Power Management Controller */
void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */
void* pvReserved7;
void* pfnUART0_Handler; /* 8 UART 0 */
void* pfnUART1_Handler; /* 9 UART 1 */
void* pvReserved10;
void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
void* pvReserved13;
void* pfnUSART0_Handler; /* 14 USART 0 */
void* pvReserved15;
void* pvReserved16;
void* pvReserved17;
void* pvReserved18;
void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */
void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */
void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */
void* pvReserved22;
void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
void* pvReserved26;
void* pvReserved27;
void* pvReserved28;
void* pfnADC_Handler; /* 29 Analog To Digital Converter */
void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
void* pfnPWM_Handler; /* 31 Pulse Width Modulation */
} DeviceVectors;
/* Peripheral typedefs */
typedef struct {
__IO uint32_t PER; /* PIO Enable Register */
__IO uint32_t PDR; /* PIO Disable Register */
__IO uint32_t PSR; /* PIO Status Register */
uint32_t Reserved0[1];
__IO uint32_t OER; /* Output Enable Register */
__IO uint32_t ODR; /* Output Disable Register */
__IO uint32_t OSR; /* Output Status Register */
uint32_t Reserved1[1];
__IO uint32_t IFER; /* Glitch Input Filter Enable Register */
__IO uint32_t IFDR; /* Glitch Input Filter Disable Register */
__IO uint32_t IFSR; /* Glitch Input Filter Status Register */
uint32_t Reserved2[1];
__IO uint32_t SODR; /* Set Output Data Register */
__IO uint32_t CODR; /* Clear Output Data Register */
__IO uint32_t ODSR; /* Output Data Status Register */
__IO uint32_t PDSR; /* Pin Data Status Register */
__IO uint32_t IER; /* Interrupt Enable Register */
__IO uint32_t IDR; /* Interrupt Disable Register */
__IO uint32_t IMR; /* Interrupt Mask Register */
__IO uint32_t ISR; /* Interrupt Status Register */
__IO uint32_t MDER; /* Multi-driver Enable Register */
__IO uint32_t MDDR; /* Multi-driver Disable Register */
__IO uint32_t MDSR; /* Multi-driver Status Register */
uint32_t Reserved3[1];
__IO uint32_t PUDR; /* Pull-up Disable Register */
__IO uint32_t PUER; /* Pull-up Enable Register */
__IO uint32_t PUSR; /* Pad Pull-up Status Register */
uint32_t Reserved4[1];
__IO uint32_t ABSR; /* Peripheral AB Select Register */
uint32_t Reserved5[3];
__IO uint32_t SCIFSR; /* System Clock Glitch Input Filter Select Register */
__IO uint32_t DIFSR; /* Debouncing Input Filter Select Register */
__IO uint32_t IFDGSR; /* Glitch or Debouncing Input Filter Clock Status Register */
__IO uint32_t SCDR; /* Slow Clock Divider Debouncing Register */
} PIO_TypeDef;
/* Peripheral instances */
#define PIOA ((PIO_TypeDef *)PIOA_BASE)
#define PIOB ((PIO_TypeDef *)PIOB_BASE)
#define PIOC ((PIO_TypeDef *)PIOC_BASE)
/* Cortex-M3 Processor exceptions definitions */
typedef struct {
__IO uint32_t ISER[8]; /* Interrupt Set Enable Registers */
uint32_t Reserved0[24];
__IO uint32_t ICER[8]; /* Interrupt Clear Enable Registers */
uint32_t Reserved1[24];
__IO uint32_t ISPR[8]; /* Interrupt Set Pending Registers */
uint32_t Reserved2[24];
__IO uint32_t ICPR[8]; /* Interrupt Clear Pending Registers */
uint32_t Reserved3[24];
__IO uint32_t IABR[8]; /* Interrupt Active Bit Registers */
uint32_t Reserved4[56];
__IO uint8_t IP[240]; /* Interrupt Priority Registers */
uint32_t Reserved5[644];
__IO uint32_t STIR; /* Software Trigger Interrupt Register */
} NVIC_Type;
/* NVIC base address */
#define NVIC_BASE (0xE000E100UL)
#define NVIC ((NVIC_Type *)NVIC_BASE)
/* System Control Block (SCB) definitions */
typedef struct {
__IO uint32_t CPUID; /* CPU ID Base Register */
__IO uint32_t ICSR; /* Interrupt Control and State Register */
__IO uint32_t VTOR; /* Vector Table Offset Register */
__IO uint32_t AIRCR; /* Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /* System Control Register */
__IO uint32_t CCR; /* Configuration and Control Register */
__IO uint8_t SHP[12]; /* System Handler Priority Registers */
__IO uint32_t SHCSR; /* System Handler Control and State Register */
__IO uint32_t CFSR; /* Configurable Fault Status Register */
__IO uint32_t HFSR; /* HardFault Status Register */
__IO uint32_t DFSR; /* Debug Fault Status Register */
__IO uint32_t MMFAR; /* MemManage Fault Address Register */
__IO uint32_t BFAR; /* BusFault Address Register */
__IO uint32_t AFSR; /* Auxiliary Fault Status Register */
__IO uint32_t PFR[2]; /* Processor Feature Registers */
__IO uint32_t DFR; /* Debug Feature Register */
__IO uint32_t ADR; /* Auxiliary Feature Register */
__IO uint32_t MMFR[4]; /* Memory Model Feature Registers */
__IO uint32_t ISAR[5]; /* Instruction Set Attributes Registers */
} SCB_Type;
/* SCB base address */
#define SCB_BASE (0xE000ED00UL)
#define SCB ((SCB_Type *)SCB_BASE)
#ifdef __cplusplus
}
#endif
#endif /* SAM3XA_H */
For the FreeRTOS I am using the latest version (FreeRTOSv202406.01-LTS) and I used the port files provided by FreeRTOS for GCC CM3. I did add hook.c and the code is as follows:
#include <FreeRTOS.h>
#include <task.h>
#include "core_cm3.h"
//------------------------------------------------------------------------------
/** Blink error pattern
*
* \param[in] n number of short pulses
*/
void blink(uint32_t n)
{
for ( uint32_t i=0; i < n; i++ )
{
PIOB->PIO_SODR = (1 << 27); // Set pin high
for (volatile int i = 0; i < 20000; i++); // Delay
PIOB->PIO_CODR = (1 << 27); // Set pin low
for (volatile int i = 0; i < 20000; i++); // Delay
}
}
//------------------------------------------------------------------------------
/** vAssertBlink
* Blink one short pulse every two seconds if configASSERT fails.
*/
void vAssertBlink()
{
blink(1);
}
//------------------------------------------------------------------------------
void __attribute__((weak)) vApplicationTickHook()
{
}
//------------------------------------------------------------------------------
void __attribute__((weak)) vApplicationIdleHook( void )
{
void main();
main();
}
//------------------------------------------------------------------------------
void vApplicationMallocFailedHook()
{
blink(2);
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName)
{
(void) pcTaskName;
(void) pxTask;
blink(3);
}
//------------------------------------------------------------------------------
/** Hard fault - blink four short flash every two seconds */
void HardFault_Handler() { blink(1); }
/** Bus fault - blink five short flashes every two seconds */
void BusFault_Handler() { blink(5); }
/** Usage fault - blink six short flashes every two seconds */
void UsageFault_Handler() { blink(6); }
FreeRTOSConfig.h
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <stdint.h>
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
#define configENABLE_BACKWARD_COMPATIBILITY 0
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 84000000 )
#define configTICK_RATE_HZ ( ( TickType_t ) 100 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
//#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 8192 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_QUEUE_SETS 1
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_NEWLIB_REENTRANT 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4 /* 15 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x0f
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
extern void vAssertBlink();
#define configASSERT( x ) if( ( x ) == 0 ) vAssertBlink()
#endif /* FREERTOS_CONFIG_H */
Linker Script:
/* Linker script for Arduino Due (SAM3X8E) */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00080000, LENGTH = 512K /* Flash memory */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K /* SRAM */
}
/* Entry point */
ENTRY(Reset_Handler)
SECTIONS
{
/* Vector table and interrupt handlers */
.isr_vector :
{
KEEP(*(.isr_vector))
} > FLASH
/* Code and read-only data */
.text :
{
_sfixed = .;
*(.text*)
*(.text)
*(.rodata*)
*(.rodata)
_efixed = .;
} > FLASH
/* Initialized data section */
.data :
{
_srelocate = .;
__data_start__ = .; /* Alias for start of .data */
*(.data*)
*(.data)
__data_end__ = .; /* Alias for end of .data */
_erelocate = .;
} > RAM AT > FLASH
/* Uninitialized data (zeroed at startup) */
.bss :
{
_szero = .;
__bss_start__ = .; /* Alias for start of .bss */
*(.bss*)
*(COMMON)
__bss_end__ = .; /* Alias for end of .bss */
_ezero = .;
. = ALIGN(8);
_sheap = .; /* Start of heap */
. += 8192; /* Reserve 8 KB for heap */
_eheap = .; /* End of heap */
} > RAM
/* Stack pointer */
.stack (NOLOAD):
{
_estack = ORIGIN(RAM) + LENGTH(RAM);
} > RAM
/* End of memory regions */
_end = .;
}
Any help would be greatly appreciated.
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