Reputation: 1
All reads from the I2C controller return 0x50085008, for example
(volatile unsigned long*)(0x21A0000+0x04); // (I2C1_IFDR)
What has to be initialized to access the I2C controller registers as described in Chapter 35 of the i.MX 6Dual/6Quad Applications Processor Reference Manual? Section 35.5.1 "Initialization sequence" assumes that other prerequistes have been met. These are the ones I set so far: 1: MUX: 2 assignments like this
*(unsigned long*)(0x20E03B8) = 0x4001b8b1; // (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21) and 28
2: clock: this looks ok but is it? (runtime output) CCM_CSCMR1: 0x20C401C = 0x900000 3: imx6 "AHB to IP Bridge (AIPSTZ): (runtime output) AIPSTZ2_MPR: 0x217C000 = 0x77777777 4: page tables for virtual to physical addressing, virtual=physical,
ldr r2, =0x00A02c02 /* Peripheral 2 region */
Possibly a clue... barebox has trouble reading memory in the address range assigned to the three I2C controllers:
barebox@PHYTEC phyCORE-i.MX6 Quad with NAND:/ md -l 0x219FFF0+0x20
0219fff0: 00000000 00000000 00000000 00000000 ................
021a0000: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ................
barebox@PHYTEC phyCORE-i.MX6 Quad with NAND:/ md -l 0x21abff0+0x20
021abff0: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ................
021ac000: 00000000 00000000 00000000 00000000 ................
Another clue... The I2C controllers are in AIPS-2. I successfully control (bare metal) LEDs attached to GPIOs in AIPS-1.
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