Reputation: 11
#define TIMEOUT 1000000 // Timeout value to avoid infinite loops
/* System Clock Configuration */
void cfg_sys_clock()
{
uint32_t timeout;
//select 8khz as MSI
MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, _VAL2FLD(RCC_CR_MSIRANGE, 0x7));
// 1. Enable MSI
SET_BIT(RCC->CR, RCC_CR_MSION);
// 2. Wait for HSI Ready
timeout = TIMEOUT;
while (!(READ_BIT(RCC->CR, RCC_CR_MSIRDY)) && --timeout);
if (timeout == 0) while (1); // Hang in case of failure
// 3. Configure PLL
MODIFY_REG(RCC->PLLCFGR,
RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |RCC_PLLCFGR_PLLR,
RCC_PLLCFGR_PLLSRC_MSI | _VAL2FLD(RCC_PLLCFGR_PLLM, 1) |
_VAL2FLD(RCC_PLLCFGR_PLLN, 24) | _VAL2FLD(RCC_PLLCFGR_PLLR, 2)
);
// 4. Enable PLL
SET_BIT(RCC->CR, RCC_CR_PLLON);
// 5. Wait for PLL Ready
timeout = TIMEOUT;
while (!(READ_BIT(RCC->CR, RCC_CR_PLLRDY)) && --timeout);
if (timeout == 0) while (1); // Hang in case of failure
// 6. Set PLL as system clock
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
// 7. Wait until PLL is used as system clock
timeout = TIMEOUT;
while ((READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) && --timeout);
if(timeout == 0) while (1); // Hang in case of failure
// 8. Set AHB and APB prescalers (No division)
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1);
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_CFGR_PPRE1_DIV1);
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_CFGR_PPRE2_DIV1);
}
flash latency is correctly set to 4ws , and board using is B-L4S5I-IOT01A stm32 controller - STM32L4S5VIT6, My code gets stuck in while loop at comment number 7 when waiting for status to to select the system clock as PLL clock ?
Upvotes: 1
Views: 50
Reputation: 1213
Always start debugging with reading out content of relevant registers (here besides RCC also the register setting FLASH waitstates) and checking their content.
My guess is, that you don't have RCC_PLLCFGR.PLLREN set.
Upvotes: 0