John Källén
Reputation: 7973
Are the AArch32 `ldc/stc` instructions restricted to using CR5?
I'm maintaining a disassembler for ARM and using the document ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (available here) as guidance.
The section System register load/store clearly specifies that bits 12-15 inclusive are used for the field CRd, but according to the table in that section, only the encoding 0101 is allocated. I'm pretty sure that earlier versions of the architecture supported an arbitrary value for this four-bit field.
Should my disassembler treat the CRd field as restricted to 0101, or should it be more permissive and allow all 16 possible values? Also, in the restricted case, what exectly is the 5'th CR in the processor?
Upvotes: 1
Views: 49
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