STM32H725ZGT6 suspected erratum in interrupt table documentation

Question

I am using the STM32H725ZGT6 for a new client application. I have used this chip before many times. This application needs 3 UARTs running. I am using USART1, UART7, USART10. I have not used USART10 on this chip before. I code all the same -- interrupt service on RX (which puts the received byte in a buffer) but polled output. USART1 and UART7 behave textbook. USART10 does not interrupt. It runs fine polled, but acts as if I am enabling the wrong interrupt bit. I have seen (web searches) some indication that some STM32 types have errata in the documentation of the interrupt table -- an offset by one address. I have tried several nearby offsets, nothing works. I have seen nothing in the ST errata, and there are no recently updated versions of the ref manual. I am using vector 0x02B0 for USART10 and enabling #156 by turning on bit #28 of NVIC_ISER4. Any help is appreciated. Jeff Casey / Rockfield Research Inc. Cedar City Utah