CODEWITHSUNDEEP
simulationsystem-verilogformal-verificationsystem-verilog-assertions
user2979872
user2979872

Reputation: 467

What is the difference between ##1 and |=> in System Verilog assertions and if statement vs assert statement?

Are there major differences between using ##1 and |=> in System Verilog assertions

A ##1 B and A => B. When do they behave similarly, and when do they differ? For example

property p_a_then_b;
  a ##1 b;  
endproperty

versus

property p_a_implies_b;
  a |=> b;  
endproperty

The second question is when to use an if statement vs an assert statement.

if (a==b)
 $display("pass");
else
$error("Error");

versus

assert(a == b);

All these questions are in the context of simulation-based verification. Would anything change if the context is Formal verification?

Upvotes: 0

Views: 17

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