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Hayri Uğur Koltuk
Hayri Uğur Koltuk

Reputation: 3020

Are ARM instructuons SWI and SVC exactly same thing?

ARM assembly has SWI and SVC instructions for entering into 'supervisor mode'.

What confuses me is, why there are two of them? Here it is said that SVC was formerly SWI. Does it mean that basically they changed the mnemonic? Are they the same thing? Can I use them interchangeably? Does one of them exist before an architecture, and other after?

Upvotes: 23

Views: 12207

Answers (2)

Ciro Santilli
Ciro Santilli

Reputation: 4053

There is a good UAL (Unified Assembler Syntax) vs pre-UAL mnemonic table on ARMv8 Appendix K6 "Legacy Instruction Syntax for AArch32 Instruction Sets"

One of the entries of that table is:

Pre-UAL syntax    UAL equivalent
SWI               SVC

which explicitly states that they are equivalent.

On GNU GAS, you can select the UAL syntax with .syntax unified.

From GCC, you can use the option -masm-syntax-unified for inline assembly, although it wasn't working in 8.2.0 due to a then fixed bug: How to write .syntax unified UAL ARMv7 inline assembly in GCC?

UAL vs pre-UAL also has further implications besides the names of certain instructions, e.g. the requirement for # or not in certain integer literals: Is the hash required for immediate values in ARM assembly?

Upvotes: 9

Kamyar Souri
Kamyar Souri

Reputation: 1923

Yes, SWI and SVC are same thing, it is just a name change. Previously, the SVC instruction was called SWI, Software Interrupt.

The opcode for SVC (and SWI) is partially user defined (bits 0-23 are user defined and are like a parameter to the SVC handler). Bits 24-27 are b1111 and these 4 bits make the CPU realize that the opcode is SVC (or SWI).
see ARM Information Center for more details.

Upvotes: 30

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