CODEWITHSUNDEEP
dma
user1110773
user1110773

Reputation: 13

DMA Transfer Data Rate

I'm trying to learn about DMA transfer rates and I don't understand this questions. I have the answers but don't know how to get there.

This question concerns the use of DMA to handle the input and storage in memory of data arriving at an input interface, the achievable data rates that can achieved using this mechanism, and the bus bandwidth (capacity) used for particular data rates. You are given details of the execution of the clock cycles executed for each DMA transfer, and the clock cycles to acquire and release the busses. Below you are given: the number of clock cycles required for the DMA device to transfer a single data item between the input interface and memory, the number of clock cycles to acquire and releases the system busses, the size (in bits) of each data item, and the clock frequency.

number of clock cycles for each data transfer 8

number of clock cycles to acquire and release busses 4

number of bits per data item = 8

clock frequency = 20MHz

A) What is the maximum achievable data rate in Kbits/second?

B) What percentage of the bus clocks are used by the DMA device if the data rate is 267Kbits/sec?

Answers

A)20000.0

B)2.0

Thanks in advance.

Upvotes: 1

Views: 12485

Answers (2)

vetri
vetri

Reputation: 1029

There are two modes to Transfer Data using DMA

1.Burst Mode

Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU. CPU is disabled to use Memory Bus for long time.it will not release bus access until entire Block of Data Transferred.

2.Cycle Stealing Mode

Once the DMA controller is granted access to the system bus by the CPU,it transfer the one byte of data then it releases the memory access to cpu . again for another byte of transfer it has to acquire bus access by cpu via BR and BG signal(BUS REQUEST and BUS GRANT).For Every Byte of Transfer it acquires bus access and releases it until entire Block of Data Transferred.

In the Above Example

Clock Frequency is 20MHZ (hz is cycles per second).20 million clock cycles per second.(20 x 10^6 cycles /second )

For Every Byte of Transfer B/W IO Interface and Memory takes 8 clock cycles. There are 20 x 10^6 Clock Cycles.In Cycle Stealing Mode For Every One Byte of Transfer it has to take another 4 clock cycles to For Bus Grant and release Access. So to Transfer One Byte Between IO Interface and Memory, 12 clock cycles are Required. Here 2/3 of clock cycles are used for Data Transfer and 1/3 of Clock Cycles are Used For Bus Access. Here One Clock Cycle is Used to Transfer One Bit of Data. 2/3 of 20 Million Clock Cycles are Used to Transfer Data and 1/3 of 20 Million Clock Cycles are Used for Bus Access.So, 13333.333 Kbits are Transferred b/w IO interface and Memory . If we take 2% from the 13333 Kb/sec approximately it will be 267 Kb/sec. Max Achievable Data Rate in this mode is 13333 Kb/s .

In Burst Mode once DMA Acquired the Bus it will release the Bus After Entire Transfer.20000 x 10^3 clock cycles are used to Transfer 20000 x 10^3 bits which is 20000 kb/sec.4 clock cycles are used for bus access. approximately it will be 20000 Kb/s

Upvotes: 6

koko
koko

Reputation: 335

To find the maximum achievable data rate, you need to divide the number of bits by the length of the process so: number of bits per data item / number of clock cycles for each data transfer * clock frequency * 1000

I'm stuck on the second part so if you managed to find the answer, please share :)

Upvotes: 0

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