CODEWITHSUNDEEP
makefilegnu-make
Mike
Mike

Reputation: 1319

Target substitution in Makefile

In a typical regression, there is a CATEGORY which is "basic" and a test-case "abc.c". To run a test "abc" in category "basic", the user has to key in:

    make basic_abc

Then the command should be:

    basic_abc: abc.c
        gcc -g -o abc abc.c

How can I write a rule, that WILL CHOP "basic_" in my $@. So that I can use the rule for all tests. In pseudo language, how can I get the above rule with pattern substitution

    basic_abc: $(patsubst .*_, " ", $@).c
        gcc -g -o  $(patsubst .*_, " ", $@)    $(patsubst .*_, " ", $@).c

Upvotes: 1

Views: 2746

Answers (1)

tripleee
tripleee

Reputation: 189457

Do you mean like this?

.PHONY: basic_%
basic_%: %.c
        gcc -g -o $* $<

Make already knows how to compile a .c file, though. From your question it would seem to make more sense for basic_x to depend on the compiled x, and run it on a bunch of test cases in the recipe, but maybe I misunderstand your setup.

Upvotes: 1

Related Questions