CODEWITHSUNDEEP
makefile
Renjith G
Renjith G

Reputation: 6707

What do $< and $@ represent in a Makefile?

Can anybody please explain the meaning of $< and $@ in a Makefile?

Upvotes: 17

Views: 2731

Answers (2)

Laurence Gonsalves
Laurence Gonsalves

Reputation: 143064

$@ is the target of the current rule. $< is the name of the first prerequisite ("source") of the current rule.

So for example:

.c.o:
        $(CC) -c $(CFLAGS) -o $@ $<

This will expand to a command something like:

gcc -c -Wall -o foo.o foo.c

See also the GNU make manual § 10.5.3, "Automatic Variables".

Upvotes: 7

Andy White
Andy White

Reputation: 88345

$< evaluates to the first "prerequisite" in the make rule, and $@ evaluates to the "target" in the make rule.

Here's an example:

file.o : file.c
        $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

In this case, $< will be replaced with file.c and $@ will be file.o.

These are more useful in generic rules like this:

%.o : %.c
        $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

See this manual for more info.

Upvotes: 26

Related Questions