CODEWITHSUNDEEP
verilog
fiftyplus
fiftyplus

Reputation: 561

Verilog, can i assign a bit value to multiple bits inside always block

Below is the code:

always @ (C[n-1])
begin
   C[2*n-1:n]=C[n-1];
end

Is that possible? If not, how can I do it? Basically it's performing a sign extension.

Upvotes: 3

Views: 5185

Answers (1)

Ben Jackson
Ben Jackson

Reputation: 93720

The syntax for replicating a bit in Verilog is {COUNT{bits}}. In your case something like {n{C[n-1]}}

Upvotes: 5

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