CODEWITHSUNDEEP
makefile
bph
bph

Reputation: 11258

Using make to build several binaries

I want to create a Makefile (in a parent dir) to call several other Makefiles (in sub dirs) such that I can build several binaries (one per project sub dir) by invoking just the one parent Makefile.

My research has been hampered by finding loads of stuff on recursive Makefiles, but I think this is where you are trying to build several directories Makefiles into a single binary?

Maybe what I want to do is better handled by a shell script perhaps invoking make in each sub directory in turn, but I thought a Makefile might be a more elegant solution?

any pointers gratefully received

PS using linux and the GNU tool chain

Upvotes: 2

Views: 4064

Answers (4)

MadScientist
MadScientist

Reputation: 100836

The for loop solution given in the first answer above actually shouldn't be used, as-is. In that method, if one of your sub-makes fails the build will not fail (as it should) but continue on with the other directories. Not only that, but the final result of the build will be whatever the exit code of the last subdirectory make was, so if that succeeded the build succeeds even if some other subdirectory failed. Not good!!

You could fix it by doing something like this:

all: 
        @for dir in $(SUBDIRS); \
        do \
            $(MAKE) -C $${dir} $@ || exit $$?; \
        done

However now you have the opposite problem: if you run "make -k" (continue even if there are errors) then this won't be obeyed in this situation. It'll still exit on failure.

An additional issue with both of the above methods is that they serialize the building of all subdirectories, so if you enable parallel builds (with make's -j option) that will only happen within a single subdirectory, instead of across all subdirectories.

Eregrith and sinsedrix have solutions that are closer to what you want, although FYI you should never, ever use "make" when you are invoking a recursive make invocation. As in johfel's example you should ALWAYS use $(MAKE).

Something like this is what you want:

SUBDIRS = subdir1 subdir1 subdir3 ...

all: $(addprefix all.,$(SUBDIRS))
all.%:
        @ $(MAKE) -C '$*' '$(basename $@)'
.PHONY: $(addprefix all.,$(SUBDIRS))

And of course you can add more stanzas like this for other targets such as "install" or whatever. There are even more fancy ways to handle building subdirectories with any generic target, but this requires a bit more detail.

If you want to support parallel builds you may need to declare dependencies at this level to avoid parallel builds of directories which depend on each other. For example in the above if you cannot build subdir3 until after both subdir1 and subdir2 are finished (but it's OK for subdir1 and subdir2 to build in parallel) then you can add something like this to your makefile:

all.subdir3 : all.subdir1 all.subdir2

Upvotes: 3

moooeeeep
moooeeeep

Reputation: 32502

you should indeed use cmake to generate the Makefile automatically from a given CMakeLists.txt configuration file.

Here's a random link to get you started. Here you can find a simple sample project, including multiple subdirectories, executables, and a shared library.

Upvotes: 0

sinsedrix
sinsedrix

Reputation: 4775

Each makefile can have several target, it's still true with recursive makefiles, usually it's written:

all: target1 target2 target3

target1 :
    make -C subdir

Then make all

Upvotes: -1

jofel
jofel

Reputation: 3405

You can call targets in subdirectory makefiles via

all: 
    $(MAKE) -C subdirectory1 $@
    $(MAKE) -C subdirectory2 $@
   ...

or better

SUBDIRS=subd1 subd2 subd3

all: 
    @for dir in $(SUBDIRS); \
    do \
      $(MAKE) -C $${dir} $@; \
    done

Upvotes: 0

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