CODEWITHSUNDEEP
verilogsystem-verilog
doddy
doddy

Reputation: 605

Gate and switch delay statements in real time or clock cycles?

I've been reading through a nice tutorial and have a quick question concerning something on pages 55-56. I'll just drag and drop the text below:

Gate and Switch delays
In real circuits, logic gates have delays associated with them. Verilog provides the
mechanism to associate delays with gates.

  *Rise, fall and Turn-off delays
  *Minimal, Typical, and Maximum delays.

Rise Delay
  The rise delay is ... etc

Min value
  The min value is the minimum delay value that the gate is expected to have.

Typ Value
  ... similar to min value

Max Value
  ... similar to min value

Referring to the explanation for Min value (and Typ and Max alike), would one set the min value to a number of clock cycles (therefore integer value) or an actual real value like 10ns? Can I do both (choosing one or the other)?

Upvotes: 3

Views: 628

Answers (1)

toolic
toolic

Reputation: 62037

Gate and switch delays are time-based, not cycle based. For example, if your timescale is set to 1ns/1ns, and you specify a delay using #10, you will get a 10ns delay. These delays know nothing about any clock signals you create.

Upvotes: 2

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