CODEWITHSUNDEEP
c++makefile
Bryan Glazer
Bryan Glazer

Reputation: 852

Problems with implicit rule in make

I have the following directory structure

         (root)
  /      /      \        \
/       |       |         \
src    obj  include     bin

I would like to use an implicit rule to compile all the .cc files in root\src to .o files in root\obj.

This is my makefile so far:

basedir = .
incl = ${basedir}\include
obj = ${basedir}\obj
src = ${basedir}\src
lib = ${basedir}\lib
bin = ${basedir}\bin

CXX = gcc

LDLIBS = -lstdc++ -lmingw32 -lSDLmain -lSDL -lSDL_image -lchipmunk -lSDL_ttf \
-lSDL_mixer

LDFLAGS = -L${lib}

objects = $(addprefix ${obj}\, GameObject.o PhysicalObject.o \
Terrain.o Timer.o main.o ImageLoader.o Player.o )

sources = $(addprefix ${src}\, GameObject.cc PhysicalObject.cc \
Terrain.cc Timer.cc main.cc ImageLoader.cc Player.cc )

Cyborg : ${objects}
    ${CXX} ${objects} -o ${bin}\Cyborg.exe -L${lib} ${LDFLAGS} ${LDFLAGS}

${obj}\%.o : ${src}\%.c
    ${CXX} ${src}\$^ -c -o ${obj}\$@ 

.PHONY: clean

clean :
    rm ${bin}\Cyborg.exe ${objects}

The error that I get is make: *** No rule to make target .\obj\GameObject.o, needed by Cyborg. Stop.

Any idea what's going wrong? I'm pretty new to makefiles so this might be terribly obvious.

Upvotes: 4

Views: 913

Answers (4)

perreal
perreal

Reputation: 98118

${obj}\%.o : ${src}\%.c --> ${obj}\%.o : ${src}\%.cc

Upvotes: 0

Nemo
Nemo

Reputation: 71615

Applying all of the ideas from the comments (and adding a couple trivial ones of my own), we get:

basedir = .
incl = ${basedir}/include
obj = ${basedir}/obj
src = ${basedir}/src
lib = ${basedir}/lib
bin = ${basedir}/bin

CXX = g++

LDLIBS = -lstdc++ -lmingw32 -lSDLmain -lSDL -lSDL_image -lchipmunk -lSDL_ttf \
-lSDL_mixer

LDFLAGS = -L${lib}

objects = $(addprefix ${obj}/, GameObject.o PhysicalObject.o \
Terrain.o Timer.o main.o ImageLoader.o Player.o )

sources = $(addprefix ${src}/, GameObject.cc PhysicalObject.cc \
Terrain.cc Timer.cc main.cc ImageLoader.cc Player.cc )

Cyborg : ${objects}
    ${CXX} ${objects} -o ${bin}/Cyborg.exe -L${lib} ${LDFLAGS} ${LDFLAGS}

${obj}/%.o : ${src}/%.c
    ${CXX} $^ -c -o $@ 

.PHONY: clean Cyborg

clean :
    rm -f ${bin}\Cyborg.exe ${objects}

What does "make Cyborg" do with this Makefile?

Upvotes: 3

Beta
Beta

Reputation: 99172

This is probably going to take a few iterations.

Try some simple rules, in order of increasing complexity, and tell us the results:

./obj/GameObject.o : ./src/GameObject.cc
    @echo trying to build $@ from $<

./obj/GameObject.o : ./obj/%.o : ./src/%.cc
    @echo trying to build $@ from $<

$(objects) : ./obj/%.o : ./src/%.cc
    @echo trying to build $@ from $<

./obj/%.o : ./src/%.cc
    @echo trying to build $@ from $<

Upvotes: 1

Pavel Zhuravlev
Pavel Zhuravlev

Reputation: 2791

I had similar problem with GNU make. Try making explisit rules for your objects:

$(obj)\GameObject.o: $(src)\GameObject.cc

$(obj)\PhysicalObject.o: $(src)\PhysicalObject.cc

# and so on for each object

Upvotes: -2

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