wiizzard
wiizzard

Reputation: 152

GNU Make Including source files from target-specific variables

I tried to build two programs with one GNU Makefile by either make prog1 or make prog2. I tried to use target-specific variables to specify the source files that are exclusive to the target but test1.c nor test2.c have been build. They're only referenced on linking the executable. How to get the Makefile to compile either test1.c or test2.c?

Here are the excerpts from my Makefile:

...
prog1: PASRC = test1.c
prog2: PASRC = test2.c
...
ASRC = $(PASRC) common.c
...
OBJS = $(ASRC:.c=.o)
...
prog1: $(OBJS) prog1.elf
prog2: $(OBJS) prog2.elf
...
%elf: $(OBJS)
    $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@

Thanks in advance for your help

Upvotes: 0

Views: 325

Answers (2)

kanaka
kanaka

Reputation: 73089

Unless you have some sort of specific requirements that you haven't stated, I suggest letting make do the work for you (default rules and flags).

PROGS = prog1 prog2
COMMON_OBJS = common.o

all: $(PROGS)
prog1 prog2: % : %.o $(COMMON_OBJS)

clean:
        rm -f $(PROGS) $(PROGS:%=%.o) $(COMMON_OBJS)

You can still set CLFAGS, LDFLAGS, etc (on the command line or in the makefile) and the default rules will pick them up.

If you are using GNU make you can see all the generated and automatic rules by running:

make -n -p

It's a lot of output, so I suggest piping it to your pager of choice.

Upvotes: 0

Maxim Egorushkin
Maxim Egorushkin

Reputation: 136228

There is no need to use target specific variables. Regular dependencies should be enough:

all : prog1 prog2 # default target

prog1 : test1.o 
prog2 : test2.o 
prog1 prog2 : common.o

%.o : %.c # how to build any .o from a corresponding .c
    $(CC) -c -o $@ $(CPPFLAGS) $(CFLAGS) $< 

prog1 prog2 : % : 
    $(CC) $^ $(LDFLAGS) $(LDLIBS) -o $@

Upvotes: 2

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