Reputation: 3716
I have a master Makefile
that calls submakefiles inside directories.
Those submakefiles are generated by autotools starting from Makefile.am
and configure.ac
files.
The first target of the entire project is a shared library, while the others are executables that link against it (so there is a dependency in the main Makefile
).
The problem is that I can only see the compilation output of the shared library, while the other projects are just printing warnings and errors (just stderr
text, I believe).
I can't understand what is causing this behaviour since all the projects are called from the very same rule in the master Makefile
and all the submakefiles are autogenerated from very seemed configuration files.
The snippet of master Makefile
that compiles all the targets looks like this:
SUBDIRS = libMylib app1 app2 app3
$(SUBDIRS):
$(ECHO) "-> Building $@"
$(MAKE) -C $@
$(ECHO) "-> Build of $@ finished."
The output of "libMylib" is like:
-> Building libMylib
libtool: compile: ppc-linux-gcc -DHAVE_CONFIG_H -I. -I/opt/ELDK/ppc_8xx/usr/include/ -I/opt/ELDK/ppc_8xx/include/ -Wall -std=gnu99 -O2 -MT libMylibF1.lo -MD -MP -MF .deps/libMylibF1.Tpo -c libMylibF1.c -fPIC -DPIC -o .libs/libMylibF1.o
...
libtool: link: ppc-linux-gcc -shared -fPIC -DPIC .libs/libMylibF1.o .libs/libMylibF2.o .libs/libMylibF3.o -Wl,-rpath -Wl,/opt/ELDK/ppc_8xx/lib -Wl,-rpath -Wl,/opt/ELDK/ppc_8xx/lib -lz -lpthread -O2 -Wl,-soname -Wl,libMylib.so.0 -o .libs/libMylib.so.0.0.0
libtool: link: (cd ".libs" && rm -f "libMylib.so.0" && ln -s "libMylib.so.0.0.0" "libawmg.so.0")
libtool: link: (cd ".libs" && rm -f "libMylib.so" && ln -s "libMylib.so.0.0.0" "libMylib.so")
libtool: link: ( cd ".libs" && rm -f "libMylib.la" && ln -s "../libMylib.la" "libMylib.la" )
-> Build of libAwmg finished.
While the output of any "appN" is:
-> Building app1
app1F1.c: In function `app1F1Func1':
app1F1.c:161: warning: unused variable `varA'
app1F2.c:85: warning: `app1F2FuncX' defined but not used
-> Build of app1 finished.
Could anyone please help me?
EDIT:
I found out that I was able to see the compile stuff in "libMylib" because it is "libtoolized".
If I "libtoolize" another project, I can see the linker part of the output (libtool: link:...
).
So, considering that make
calls a shell (sh
) for each line in the rule, that $(MAKE) equals to just "make" and, by default, make
is verbose, why do the submake is not printing its output to stdout?
Which flags may be passed to it so that this happens?
Upvotes: 2
Views: 781
Reputation: 3716
Well, my master makefile includes another file that puts a .SILENT
rule in.
I haven't noticed that until today. Removing this rule makes everithing work as expected.
Oh my...
Upvotes: 1
Reputation: 3520
It depends on the Makefiles in the sub directories. If, for example, you have a @ in front of the compile commands in the app Makefiles, then they will not output the commands that were being run (also look for $(Q), which is used quite commonly when you want to enable/disable verboseness in makefiles). Alternatively, your make commands in the apps directories may be pushing stdout to some files (which would still allow you to see the warnings).
By the same token your library makefile may be incorrectly redirecting stderr elsewhere, which would explain why you don't see any error outputs on that (or it just doens't have any errors...)
Please post the build rules in the other directories (and all associated variable definitions) if you want more help.
Upvotes: 2