CODEWITHSUNDEEP
vhdl
user1260867
user1260867

Reputation: 23

VHDL setting constant data in RAM

Recently i'm using VHDL to write a 16-but RAM. My code is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.Numeric_Std.all;

entity RAM is
port(
PC_in: in std_logic_vector (5 downto 0);
EN_WR_in: in std_logic_vector (1 downto 0);
RAM_in : in std_logic_vector(15 downto 0);
RAM_out : out std_logic_vector(15 downto 0);
test : out integer
);


end RAM;

architecture Behavioral of RAM is
type ram_t is array (63 downto 0) of std_logic_vector(15 downto 0);
signal ram : ram_t;
begin
PROCESS (EN_WR_in)
BEGIN
        if (EN_WR_in(1)='1') then

        IF (EN_WR_in(0) = '1') THEN
            ram(conv_integer(unsigned(PC_in))) <= RAM_in;
             else
        RAM_out <= ram(conv_integer(unsigned(PC_in)));
        end if;

        else

        RAM_out <="ZZZZZZZZZZZZZZZZ";

        end if;

END PROCESS;
     ram(20) <= "0000100010010000";
end Behavioral;

The problem that i facing with is i need to set some constant data in the ram just like

ram(20) <= "0000100010010000";

But the constant data didn't exist during simulation. Is there any way to solve it?

Thanks.

Upvotes: 2

Views: 3892

Answers (1)

Charles Steinkuehler
Charles Steinkuehler

Reputation: 3365

You can initialize the ram when you declare it:

signal ram : ram_t := ( "0000100010010000", x"1234", ... );

or perhaps

signal ram : ram_t := ( 20 => "0000100010010000", others => (others=>'0') );

Upvotes: 5

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