Reputation: 4600
My question is deceptively simple, but I have lost several hours of study trying to get the solution. I'm trying to create a Makefile that builds an executable for each .c file in a directory.
I have tried the following:
CC = gcc
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c,%.o,$(SRCS))
all: $(OBJS)
$(CC) $< -o $@
%.o: %.c
$(CC) $(CPFLAGS) -c $<
but this way it is creating only .o
files, and not any executables. I need a rule that makes an executable for each of these .o
files. Something like the following:
gcc src.o -o src
Upvotes: 8
Views: 3572
Reputation: 11
This is the Makefile I use to compile a bunch of scheme files.
SRCS = $(wildcard *.scm)
all: $(SRCS:.scm=)
%: %.scm
chicken-csc -o $@ $<
Upvotes: 1
Reputation: 15582
Try the following:
% : %.c
$(CC) $(CFLAGS) $(CPPFLAGS) -o $@ $<
all: $(basename $(wildcard *.c))
and you don't even need the first two lines, as make
knows how to compile and link .c files into executables. Still, it is often necessary to change make
's built-in recipes.
Upvotes: 1
Reputation: 9972
rob's answer doesn't seem to work on my machine. Perhaps, as the complete Makefile:
SRCS = $(wildcard *.c)
all: $(SRCS:.c=)
.c:
gcc $(CPFLAGS) $< -o $@
(The last two lines, are on my machine, unnecessary, as the default rules are adequate.)
Upvotes: 7
Reputation: 2133
Your all
is telling it just to build the object files. Add something like
EXEC = $(patsubst %.c,%,$(SRCS))
all: $(EXEC)
Upvotes: 2