StackOverflow Questions for Tag: chisel

Fang Yongrui

Reputation: 11

In chisel6.2.0, how to use hex file to init memory and test it?

scalasbtchisel

Score: 1

Answers: 0

AlexMontgomerie

Reputation: 11

Adding an AttributeAnnotation to a SyncReadMem object in latest Chisel versions

chiselfirrtl

Score: 1

Answers: 0

Aperture Initiative

Reputation: 58

In Chisel3, how to add `mark_debug = "true"` attribute to an internal signal in the output SystemVerilog file?

chiselfirrtl

Score: 0

Answers: 1

user2065276

Reputation: 311

Chisel3 VCD waveform dump does not update a signal

chiselwaveformgtkwavechiseltest

Score: 0

Answers: 0

Саша Коваленко

Reputation: 1

How to disable `ifdef FIRRTL_BEFORE_INITIAL` in Chisel?

scalachisel

Score: 0

Answers: 1

박성수

Reputation: 11

In RISCV, is Each thread has a own PC value in multithreading Program?

clinuxcpu-architectureriscvchisel

Score: 1

Answers: 1

boat

Reputation: 13

How to generate Verilog rather than SystemVerilog from Chisel?

scalachisel

Score: 1

Answers: 1

apaj

Reputation: 309

How to obtain emulator binary in latest rocket-chip using mill and chisel 5.0.0?

verilogriscvchiselrocket-chipverilator

Score: 0

Answers: 0

Uriht

Reputation: 1

An error occured while compling chisel test - could not find implicit value for evidence parameter of type

chiselchiseltest

Score: 0

Answers: 0

m l

Reputation: 1

error message chisel when call a module in another module

classobjectnestedchisel

Score: 0

Answers: 0

BurgerMan

Reputation: 37

Chisel Template Not Functioning Windows 11 - Cannot run program "which": CreateProcess error=2, The system cannot find the file specified

scalachiselchiseltest

Score: 1

Answers: 0

Moriss

Reputation: 335

How to create a vector of vector when I'm defining IO

chisel

Score: 4

Answers: 5

Sharafat Hussain

Reputation: 29

Using each delayed flop states in chisel ShiftRegister

scalahdlchisel

Score: 3

Answers: 1

FabienM

Reputation: 3741

With Chisel How to avoid verilog file list at the end of generated file when using BlackBox?

scalaverilogchisel

Score: 0

Answers: 0

FabienM

Reputation: 3741

Is it good thing to use `reduce(_ ## _) ` for IndexedSeq to UInt conversion in Chisel?

scalareducechisel

Score: 1

Answers: 2

P. Meng

Reputation: 61

Best way to poke or expect a vector port

chisel

Score: 4

Answers: 2

Srishti Sharma

Reputation: 21

Generating verilog file for rocket chip

chiselrocket-chip

Score: 2

Answers: 1

yu-yake

Reputation: 1

How to override a Chisel constant with type of Vec?

scalachisel

Score: 0

Answers: 1

fffff

Reputation: 69

How can i generate vcd file with recent version of Chisel?

chiselchiseltest

Score: 1

Answers: 0

justin pan

Reputation: 1

An error occured while testing Queue. 'FlitTypes' must be hardware, not a bare Chisel type

chiselchiseltest

Score: 0

Answers: 0

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StackOverflow Questions for Tag: chisel

In chisel6.2.0, how to use hex file to init memory and test it?

Adding an AttributeAnnotation to a SyncReadMem object in latest Chisel versions

In Chisel3, how to add `mark_debug = &quot;true&quot;` attribute to an internal signal in the output SystemVerilog file?

Chisel3 VCD waveform dump does not update a signal

How to disable `ifdef FIRRTL_BEFORE_INITIAL` in Chisel?

In RISCV, is Each thread has a own PC value in multithreading Program?

How to generate Verilog rather than SystemVerilog from Chisel?

How to obtain emulator binary in latest rocket-chip using mill and chisel 5.0.0?

An error occured while compling chisel test - could not find implicit value for evidence parameter of type

error message chisel when call a module in another module

Chisel Template Not Functioning Windows 11 - Cannot run program &quot;which&quot;: CreateProcess error=2, The system cannot find the file specified

How to create a vector of vector when I&#39;m defining IO

Using each delayed flop states in chisel ShiftRegister

With Chisel How to avoid verilog file list at the end of generated file when using BlackBox?

Is it good thing to use `reduce(_ ## _) ` for IndexedSeq to UInt conversion in Chisel?

Best way to poke or expect a vector port

Generating verilog file for rocket chip

How to override a Chisel constant with type of Vec?

How can i generate vcd file with recent version of Chisel?

An error occured while testing Queue. &#39;FlitTypes&#39; must be hardware, not a bare Chisel type

In Chisel3, how to add `mark_debug = "true"` attribute to an internal signal in the output SystemVerilog file?

Chisel Template Not Functioning Windows 11 - Cannot run program "which": CreateProcess error=2, The system cannot find the file specified

How to create a vector of vector when I'm defining IO

An error occured while testing Queue. 'FlitTypes' must be hardware, not a bare Chisel type