StackOverflow Questions for Tag: ice40

Richard Vodden

Reputation: 369

Cannot get yosys to infer BRAM

verilogyosysice40

Score: 0

Answers: 1

jsmith95

Reputation: 13

How to program Lattice iCE40 ultra with a microcontroller

cfpgastm32f4ice40

Score: 1

Answers: 2

farindk

Reputation: 260

Yosys optimizes away ring oscillator on ice40 FPGA

fpgayosysice40

Score: 1

Answers: 1

zapta

Reputation: 125

How to reset the RTL on power up for the Lattice ICE40 FPGA?

verilogice40

Score: 0

Answers: 1

Renato

Reputation: 190

Error when instantiating SB_IO_D for Lattice ICE40 for input in VDHL

vhdllatticeice40

Score: 1

Answers: 1

nalzok

Reputation: 16117

Understanding the SB_IO primitive in Lattice ICE40

verilogfpgalatticeyosysice40

Score: 2

Answers: 3

gus

Reputation: 365

Verilog Coding Not Performing as Expected

verilogregister-transfer-levelice40

Score: 0

Answers: 1

gus

Reputation: 365

Use PLL in Lattice Radiant

vhdlregister-transfer-levelice40

Score: 0

Answers: 1

N.Atema

Reputation: 113

Using the SB_RGBA_DRV primitive in VHDL

vhdlice40

Score: 3

Answers: 2

Neekon Saadat

Reputation: 417

Yosys: Multiple edge sensitivities for asynchronous reset

verilogsignal-processingfpgayosysice40

Score: 2

Answers: 1

Damien

Reputation: 1552

Verilog ICE40 LED Driver as IO - SB_IO_OD, how to assign

verilogfpgaice40

Score: 0

Answers: 1

ke10g

Reputation: 27

Trouble getting YOSYS to infer block ram array (rather than using logic cells) verilog ice40

verilogramyosysice40

Score: 0

Answers: 3

TinLethax

Reputation: 11

Cascading BRAM in iCE40 FPGA

verilogfpgalatticehdlice40

Score: 0

Answers: 2

wombatbutt

Reputation: 1

USB Errno 5 when uploading to a TinyFPGA BX with tinyprog

pythonfpgaice40

Score: 0

Answers: 0

71GA

Reputation: 1391

iCE40 Ultra Plus 5k -- how to set PLL (without propietary GUI tools)

vhdlfpgaice40

Score: 0

Answers: 1

TerryL

Reputation: 1

Xilinx equivalent primitive of ICE40 SB_IO primitive?

fpgaxilinxequivalentice40

Score: 0

Answers: 1

Carlos J.

Reputation: 11

JK-flip flop using gate level description in Verilog give me a timming error

verilogfpgaice40

Score: -2

Answers: 1

Sajjad

Reputation: 121

Understanding Organization of the CRAM bits in bitstream .bin file

yosysice40

Score: 0

Answers: 1

ke10g

Reputation: 27

reading multiple block ram indexes in one write clock cycle

arraysverilogramyosysice40

Score: 0

Answers: 1

Dave

Reputation: 23

ice40 clock delay, output timing analysis

verilogfpgayosysice40

Score: 0

Answers: 1

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